| 國立臺灣大學 |
2007 |
A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop
|
Kao, Shao-Ku; Chen, Bo-Jiun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
Spur-suppression techniques for frequency synthesizers
|
Liang, Che-Fu; Chen, Hsin-Hua; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 2.5GHz all-digital delay-locked loop in 0.13μm CMOS technology
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A DLL-based variable-phase clock buffer
|
Chen, Chao-Chyun; Chang, Jung-Yu; Liu, Shen-Iuan |
| 淡江大學 |
2006-07 |
Magnetic-field-to-digital converter using PWM and TDC techniques
|
郭建宏; Kuo, Chien-hung; Chen, Shr-lung; Liu, Shen-iuan |
| 國立臺灣大學 |
2006-02 |
CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique
|
Wu, Chia-Hsin; Lee, Chih-Hun; Chen, Wei-Sheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A spur-reduction technique for a 5-GHz frequency synthesizer
|
Kuo, Chun-Yi; Chang, Jung-Yu; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 ?m CMOS Technology
|
CHUANG, Chi-Nan; LIU, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 200-Mbps∼ 2-Gbps continuous-rate clock-and-data-recovery circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop
|
Chang, Hsiang-Hui; Chang, Jung-Yu; Kuo, Chun-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Hwu, Sy-Chyuan; Liang, Chuan-Kang; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles
|
Wang, You-Jen; Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A Calibrated Pulse Generator for Impulse-Radio UWB Applications
|
Liang, Che-Fu; Liu, Shih-Tsai; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
All-digital fast-locked synchronous duty cycle corrector
|
Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005-09 |
A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 淡江大學 |
2005-05-23 |
A tunable bandpass ΔΣ modulator using double sampling
|
郭建宏; Kuo, Chien-hung; Chen, Chang-hung; Huang, Shih-lin; Liu, Shen-iuan |
| 國立臺灣大學 |
2005-05 |
A 15mW 69dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications
|
Lee, Hua-Chin; Lin, Chien-Chih; Wu, Chia-Hsin; Liu, Shen-Iuan; Wang, Chorng-Kuang; Tsao, Hen-Wai |
| 國立臺灣大學 |
2005-03 |
A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop
|
Chang, Hsiang-Hui; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005-03 |
CMOS Current-Mode Divider and Its Applications
|
Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken |
| 臺大學術典藏 |
2005-03 |
CMOS Current-Mode Divider and Its Applications
|
Wei, Shui-Ken; Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken; Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
CMOS wideband amplifiers using multiple inductive-series peaking technique
|
Wu, Chia-Hsin; Lee, Chih-Hun; Chen, Wei-Sheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A single-path pulsewidth control loop with a built-in delay-locked loop
|
Han, Sung-Rung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A wide-range multiphase delay-locked loop using mixed-mode VCDLs
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
