| 國立臺灣大學 |
2008 |
A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
10-Gb/s Inductorless CDRs With Digital Frequency Calibration
|
Liang, Che-Fu; Chu, Hong-Lin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A delay-locked loop with statistical background calibration
|
Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line
|
Chen, Chao-Chyun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs
|
Lin, Shao-Hung; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:34:31Z |
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution
|
Chen, Poki;Liu, Shen-Iuan; Chen, Poki; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:12:30Z |
CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure
|
Wu, Yan-Pei; Chen, Jiann-Jong; Liu, Shen-Iuan; Tsay, Jiann-Horng; Tsay, Jiann-Horng; Liu, Shen-Iuan; Chen, Jiann-Jong; Wu, Yan-Pei |
| 國立臺灣大學 |
2007 |
A time-constant calibrated phase-locked loop with a fast-locked time
|
Han, Sung-Rung; Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A CMOS 5-bit 5GSample/sec analog-to-digital converter in 0.13um CMOS
|
Wang, I-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS
|
Chen, Ke-Hou; Lu, Jian-Hao; Chen, Bo-Jiun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A multi-band burst-mode clock and data recovery circuit
|
Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A capacitor multiplication technique using a second-generation current conveyor in the loop filter of the phase-locked loops
|
Chen, Chao-Chyun; Lee, Sheng-Chou; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology
|
Cho, Lan-Chou; Lee, Chihun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop
|
Kao, Shao-Ku; Chen, Bo-Jiun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
Spur-suppression techniques for frequency synthesizers
|
Liang, Che-Fu; Chen, Hsin-Hua; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 2.5GHz all-digital delay-locked loop in 0.13μm CMOS technology
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A DLL-based variable-phase clock buffer
|
Chen, Chao-Chyun; Chang, Jung-Yu; Liu, Shen-Iuan |
| 淡江大學 |
2006-07 |
Magnetic-field-to-digital converter using PWM and TDC techniques
|
郭建宏; Kuo, Chien-hung; Chen, Shr-lung; Liu, Shen-iuan |
| 國立臺灣大學 |
2006-02 |
CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique
|
Wu, Chia-Hsin; Lee, Chih-Hun; Chen, Wei-Sheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A spur-reduction technique for a 5-GHz frequency synthesizer
|
Kuo, Chun-Yi; Chang, Jung-Yu; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 ?m CMOS Technology
|
CHUANG, Chi-Nan; LIU, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 200-Mbps∼ 2-Gbps continuous-rate clock-and-data-recovery circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Liu, Shen-Iuan |
