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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"liu shen iuan"的相關文件
顯示項目 41-50 / 185 (共19頁)
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| 國立臺灣大學 |
2008 |
A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
10-Gb/s Inductorless CDRs With Digital Frequency Calibration
|
Liang, Che-Fu; Chu, Hong-Lin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A delay-locked loop with statistical background calibration
|
Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line
|
Chen, Chao-Chyun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs
|
Lin, Shao-Hung; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:34:31Z |
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution
|
Chen, Poki;Liu, Shen-Iuan; Chen, Poki; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:12:30Z |
CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure
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Wu, Yan-Pei; Chen, Jiann-Jong; Liu, Shen-Iuan; Tsay, Jiann-Horng; Tsay, Jiann-Horng; Liu, Shen-Iuan; Chen, Jiann-Jong; Wu, Yan-Pei |
| 國立臺灣大學 |
2007 |
A time-constant calibrated phase-locked loop with a fast-locked time
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Han, Sung-Rung; Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
顯示項目 41-50 / 185 (共19頁)
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