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Taiwan Academic Institutional Repository >
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| 國立臺灣科技大學 |
2013 |
Testable design for electrical testing of open defects at interconnects in 3D ICs
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Hashizume, M.;Konishi, T.;Yotsuyanag, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
Error-tolerance evaluation and design techniques for motion estimation computing arrays
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Lu, S.-K.;Chen, M.-C.;Chen, Y.-C. |
| 國立臺灣科技大學 |
2013 |
Efficient test and repair architectures for 3D TSV-based random access memories
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Lu, S.-K.;Lu, U.-C.;Pong, S.-W.;Cheng, H.-C. |
| 國立臺灣科技大學 |
2013 |
Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC
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Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z. |
| 國立臺灣科技大學 |
2013 |
Built-in IDDT appearance time sensor for detecting open faults in 3D IC
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Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
Fault scrambling techniques for yield enhancement of embedded memories
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Lu, S.-K.;Jheng, H.-C.;Hashizume, M.;Huang, J.-L.;Ning, P. |
| 國立臺灣科技大學 |
2013 |
DFT for supply current testing to detect open defects at interconnects in 3D ICs
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Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.;Roth, Z. |
| 國立臺灣科技大學 |
2013 |
An efficient test and repair flow for yield enhancement of one-time-programming NROM-based ROMs
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Li, T.-L.;Hashizume, M.;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
Synergistic reliability and yield enhancement techniques for embedded SRAMs
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Lu, S.-K.;Huang, H.-H.;Huang, J.-L.;Ning, P. |
| 國立臺灣科技大學 |
2012 |
Efficient built-in self-repair techniques for multiple repairable embedded RAMs
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Lu, S.-K.;Wang, Z.-Y.;Tsai, Y.-M.;Chen, J.-L. |
| 國立臺灣科技大學 |
2012 |
Improving reusability of test symbols for test data compression
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Lu, S.-K.;Huang, Y.-C. |
| 國立臺灣科技大學 |
2012 |
Scrambling and data inversion techniques for yield enhancement of NROM-Based ROMs
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Lu, S.-K.;Li, T.-L.;Ning, P. |
| 國立臺灣科技大學 |
2012 |
On test and repair of 3D random access memory
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Wu, C.-W.; Lu, S.-K.; Li, J.-F. |
| 國立臺灣科技大學 |
2012 |
Yield enhancement techniques for 3-dimensional random access memories
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Lu, S.-K.;Chang, T.-W.;Hsu, H.-Y. |
| 國立臺灣科技大學 |
2011 |
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores
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Lu, S.K.;Chen, Y.M.;Huang, S.Y.;Wu, C.W. |
| 國立臺灣科技大學 |
2009 |
Wireless built-in self-repair architectures for embedded RAMs
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Wang Z.-Y; Tsai Y.-M.; Hsiao Y.-C.; Lu S.-K. |
| 國立臺灣科技大學 |
2009 |
Built-in self-repair techniques for heterogeneous memory cores
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Wang Z.-Y.; Tsai Y.-M.; Lu S.-K. |
| 國立臺灣大學 |
1993-05 |
Enhancing testability of VLSI arrays for fast Fourier transform
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Lu, S.-K.; Wu, C.-W.; Kuo, S.-Y. |
| 國立臺灣大學 |
1992-03 |
Testable Design of Systolic Arrays for Discrete Cosine Transform
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Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen |
| 臺大學術典藏 |
1992-03 |
Testable Design of Systolic Arrays for Discrete Cosine Transform
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Wu, C. W.; Lu, S. K.; Kuo, Sy-Yen; Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Kuo, Sy-Yen |
| 國立臺灣大學 |
1992 |
Design of Easily Testable VLSI Arrays for Discrete Cosine Transform
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Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen |
| 臺大學術典藏 |
1992 |
Design of Easily Testable VLSI Arrays for Discrete Cosine Transform
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Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Lu, S. K.; Wu, C. W.; 郭斯彥; Kuo, Sy-Yen |
| 國立臺灣大學 |
1991-08 |
Design and Evaluation of Fault-Tolerant Interleaved Memory Systems
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郭斯彥; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W. |
| 臺大學術典藏 |
1991-08 |
Design and Evaluation of Fault-Tolerant Interleaved Memory Systems
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Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Liang, S. C.; 郭斯彥; Liang, S. C.; Louri, A.; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen |
| 國立臺灣大學 |
1988 |
Reproduction of Lobsters
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Lu, S. K.; 郭欽明; Lu, S. K.; Kuo, Ching-Ming |
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