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Showing items 51-60 of 78  (8 Page(s) Totally)
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Institution Date Title Author
義守大學 2010-08 Design and Implementation of Readout Circuit on Glass Substrate for Touch Panel Applications Tzu-Ming Wang;Ming-Dou Ker
義守大學 2010-07 High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process Ming-Dou Ker;Chun-Yu Lin
義守大學 2010-06 Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology Shih-Hung Chen;Ming-Dou Ker
義守大學 2010-06 Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme Chun-Yu Lin;Ming-Dou Ker;Yuan-Wen Hsiao
義守大學 2010-06 Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits Chih-Ting Yeh;Ming-Dou Ker;Yung-Chih Liang
義守大學 2010-06 Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology Chang-Tzu Wang;Ming-Dou Ker
義守大學 2010-05 Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process Wen-Yi Chen;Ming-Dou Ker
義守大學 2010-02 New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS Wen-Yi Chen;Ming-Dou Ker
義守大學 2010-01 Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation Hui-Wen Tsai;Ming-Dou Ker
義守大學 2009-09 New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process Ming-Dou Ker ; Wen-Yi Chen ; Wuu-Trong Shieh ; I-Ju Wei

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