臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

关于TAIR
	计画说明

浏览
	典藏机构
	作者
	题名
	日期
	统计图表
	机构即时统计
	学术趋势

消息
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

著作权
	出版社及期刊政策查询
	TAIR著作权会议记录

相关连结
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"ming dou ker"的相关文件

回到依作者浏览
依题名排序	依日期排序

显示项目 51-75 / 78 (共4页)
<< < 1 2 3 4 > >>
每页显示[10|25|50]项目

机构	日期	题名	作者
義守大學	2010-08	Design and Implementation of Readout Circuit on Glass Substrate for Touch Panel Applications	Tzu-Ming Wang;Ming-Dou Ker
義守大學	2010-07	High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process	Ming-Dou Ker;Chun-Yu Lin
義守大學	2010-06	Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology	Shih-Hung Chen;Ming-Dou Ker
義守大學	2010-06	Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme	Chun-Yu Lin;Ming-Dou Ker;Yuan-Wen Hsiao
義守大學	2010-06	Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits	Chih-Ting Yeh;Ming-Dou Ker;Yung-Chih Liang
義守大學	2010-06	Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology	Chang-Tzu Wang;Ming-Dou Ker
義守大學	2010-05	Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process	Wen-Yi Chen;Ming-Dou Ker
義守大學	2010-02	New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS	Wen-Yi Chen;Ming-Dou Ker
義守大學	2010-01	Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation	Hui-Wen Tsai;Ming-Dou Ker
義守大學	2009-09	New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process	Ming-Dou Ker ; Wen-Yi Chen ; Wuu-Trong Shieh ; I-Ju Wei
義守大學	2009-09	Design of Analog Output Buffer With Level Shifting Function on Glass Substrate for Panel Application	Tzu-Ming Wang;Ming-Dou Ker;Sao-Chi Chen
義守大學	2009-08	Transient-Induced Latchup in CMOS Integrated Circuits	柯明道;Ming-Dou Ker; Sheng-Fu Hsu
義守大學	2009-08	Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs	Ming-Dou Ker;Cheng-Cheng Yen
義守大學	2009-08	Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology	Jung-Sheng Chen;Ming-Dou Ker
義守大學	2009-07	Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection	Shih-Hung Chen;Ming-Dou Ker
義守大學	2009-06	Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process	Yuan-Wen Hsiao;Ming-Dou Ker
義守大學	2009-06	Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test	Cheng-Cheng Yen;Ming-Dou Ker;Tung-Yang Chen
義守大學	2009-06	The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps	Cheng-Cheng Yen;Ming-Dou Ker
義守大學	2009-05	Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs	Shih-Hung Chen;Ming-Dou Ker
義守大學	2009-05	A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process	Yuan-Wen Hsiao;Ming-Dou Ker
義守大學	2009-05	Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology	Tzu-Ming Wang; Ming-Dou Ker; Hung-Tai Liao
義守大學	2009-04	High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection	Wen-Yi Chen;Ming-Dou Ker
義守大學	2009-03	Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits	Ming-Dou KER;Yuan-Wen HSIAO
義守大學	2009-03	Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes	Ming-Dou Ker;Chang-Tzu Wang
義守大學	2009-03	Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology	Chang-Tzu Wang;Ming-Dou Ker

显示项目 51-75 / 78 (共4页)
<< < 1 2 3 4 > >>
每页显示[10|25|50]项目

	English \| 正體中文 \| 简体中文 \| 总笔数 :2851814
	造访人次 : 44846252 在线人数 : 1155 教育部委托研究计画计画执行:国立台湾大学图书馆