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國立臺灣科技大學 |
2020 |
High-Precision PLL Delay Matrix with Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters
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Chen, P.;Lan, J.-T.;Wang, R.-T.;My, Qui N.;Marquez, J.C.J.S.;Kajihara, S.;Miyake, Y. |
國立臺灣科技大學 |
2019 |
On-chip test clock validation using a time-to-digital converter in FPGAs
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Miyake, Y.;Kajihara, S.;Chen, P. |
Showing items 1-2 of 2 (1 Page(s) Totally) 1 View [10|25|50] records per page
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