|
English
|
正體中文
|
简体中文
|
Total items :2833128
|
|
Visitors :
34239860
Online Users :
1295
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"rau jiann chyi"
Showing items 1-10 of 44 (5 Page(s) Totally)
1 2 3 4 5 > >>
View [10|25|50] records per page
| 淡江大學 |
2021-11-16 |
A Scan-Based Lower-Power Testing Architecture for Modern Circuits
|
Rau, Jiann-Chyi;Wang, Jia-Xiang |
| 淡江大學 |
2018-04-13 |
Low-Capture-Power X-filling Method Base On Architecture Using Selection Expansion
|
Chung, Yu-Ting;Rau, Jiann-Chyi |
| 淡江大學 |
2013-06 |
Compact Test Pattern Selection for Small Delay Defect
|
Chia-Yuan Chang; Kuan-Yu Liao; Sheng-Chang Hsu; Li, J.C.; Rau, Jiann-Chyi |
| 淡江大學 |
2012-11 |
Optimal Unknown Bit Filtering for Test Response Masking
|
Weng, Ding-ke; Rau, Jiann-Chyi; Lin , Cheng-han |
| 淡江大學 |
2012-11 |
An Efficient Test Data Compression Scheme Using Selection Expansion
|
Rau, Jiann-chyi |
| 淡江大學 |
2012-11 |
Multimode ATPG for DVFS Designs
|
Bai, B.; Lin, J.; Rau, Jiann-chyi |
| 淡江大學 |
2012-10-18 |
Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
|
Shih, Chi-Jih; Hsu, Chih-Yao; Kuo, Chun-Yi; Li, James; Rau, Jiann-Chyi; Krishnendu Chakrabarty |
| 淡江大學 |
2012-06 |
Test Slice Difference Technique for Low-Transition Test Data Compression
|
Rau, Jiann-Chyi; Wu, Po-Han; Li, Wei-Lin |
| 淡江大學 |
2011-06 |
Power-aware compression scheme for multiple scan-chain
|
Rau, Jiann-Chyi; Wu, Po-Han |
| 淡江大學 |
2011-03 |
An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
|
Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han |
Showing items 1-10 of 44 (5 Page(s) Totally)
1 2 3 4 5 > >>
View [10|25|50] records per page
|
