臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:42:01Z	Loop latency reduction technique for all-digital clock and data recovery circuits	I-Fong Chen;Rong-Jyi Yang;Shen-Iuan Liu; I-Fong Chen; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:08:32Z	An all-digital fast-locking programmable DLL-based clock generator	Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T05:27:03Z	A wide-range multiphase delay-locked loop using mixed-mode VCDLs	Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T05:27:03Z	A fully integrated 1.7-3.125 Gbps clock and data recovery circuit using a gated frequency detector	Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:59:17Z	Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection	Hsiang-Hui Chang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:15:16Z	Gigahertz CMOS monolithic frequency synthesizer	Rong-Jyi Yang; Ming-Zhe Liu; Shen-Iuan Liu; SHEN-IUAN LIU
元智大學	2012-11-04	A Wide-Range All-Digital Delay-Locked Loop Using Fast-Lock Variable SAR Algorithm	Wei-Cheng Chen; Rong-Jyi Yang; Chia-Yu Yao; Chao-Chyun Chen

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