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Showing items 1-5 of 5 (1 Page(s) Totally)
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| 國立臺灣科技大學 |
2018 |
A design for testability of open defects at interconnects in 3D stacked ICs
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Ashikin F.; Hashizume M.; Yotsuyanagi H.; Lu S.-K.; Roth Z. |
| 國立臺灣科技大學 |
2016 |
A built-in electrical test circuit for detecting open leads in assembled PCB circuits
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Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z. |
| 國立臺灣科技大學 |
2016 |
A built-in test circuit for electrical interconnect testing of open defects in assembled PCBs
|
Widiant, Hashizume M;Suenaga, Suenaga S;Yotsuyanagi, H;Ono, A;Lu, S.-K;Roth, Z. |
| 國立臺灣科技大學 |
2013 |
Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC
|
Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z. |
| 國立臺灣科技大學 |
2013 |
DFT for supply current testing to detect open defects at interconnects in 3D ICs
|
Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.;Roth, Z. |
Showing items 1-5 of 5 (1 Page(s) Totally)
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