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"shiu rm"
Showing items 1-8 of 8 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:46:15Z |
Instruction cache prefetching directed by branch prediction
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Chiu, JC; Shiu, RM; Chi, SA; Chung, CP |
| 國立交通大學 |
2014-12-08T15:45:37Z |
Decoding of CISC instructions in superscalar processors with high issue rate
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Shiu, RM; Chiu, JC; Cheng, SK; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:45:16Z |
Applying stack simulation for branch target buffers
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Shiu, RM; Lu, NP; Chung, CP |
| 國立交通大學 |
2014-12-08T15:43:30Z |
Aggressive scheduling for memory accesses of CISC superscalar microprocessors
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Shiu, RM; Hwang, HY; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:27:37Z |
Register renaming for x86 superscalar design
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Liu, CC; Shiu, RM; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:30Z |
Instruction cache prefetching with extended BTB
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Chi, SA; Shiu, RM; Chiu, JC; Chang, SE; Chung, CP |
| 國立交通大學 |
2014-12-08T15:27:20Z |
Decoding unit with high issue rate for X86 superscalar microprocessors
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Cheng, SK; Shiu, RM; Shann, JJJ |
| 國立交通大學 |
2014-12-08T15:27:20Z |
An X86 load/store unit with aggressive scheduling of load/store operations
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Hwang, HY; Shiu, RM; Shann, JJJ |
Showing items 1-8 of 8 (1 Page(s) Totally)
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