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Showing items 1-25 of 31 (2 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T06:00:54Z |
A queue manager chip for shared buffer ATM switches
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Lin, YS; Huang, HC; Shung, CB |
| 國立交通大學 |
2019-04-02T06:00:53Z |
Multiple-training bi-directional adaptive equalizers for TDMA digital cellular systems
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Chen, MJ; Shung, CB |
| 國立交通大學 |
2019-04-02T05:58:27Z |
Technology mapping for FPGAs with composite logic block architectures
|
Chuang, HH; Shung, CB |
| 國立交通大學 |
2014-12-08T15:49:21Z |
An efficient architecture for multicasting in shared buffer ATM switches
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Lin, YS; Shung, CB |
| 國立交通大學 |
2014-12-08T15:49:02Z |
Design of knockout concentrators
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Lin, YS; Shung, CB; Chen, JC |
| 國立交通大學 |
2014-12-08T15:48:45Z |
A combined channel assignment mechanism for hierarchical cellular systems
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Lo, KR; Chang, CJ; Chang, C; Shung, CB |
| 國立交通大學 |
2014-12-08T15:46:43Z |
New serial architecture for the Berlekamp-Massey algorithm
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Chang, HC; Shung, CB |
| 國立交通大學 |
2014-12-08T15:45:42Z |
Two systolic architectures for modular multiplication
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Tsai, WC; Shung, CB; Wang, SJ |
| 國立交通大學 |
2014-12-08T15:44:50Z |
A QoS-guaranteed fuzzy channel allocation controller for hierarchical cellular systems
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Lo, KR; Chang, CJ; Chang, C; Shung, CB |
| 國立交通大學 |
2014-12-08T15:44:35Z |
Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs
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Chuang, HH; Jou, JY; Shung, CB |
| 國立交通大學 |
2014-12-08T15:44:14Z |
A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications
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Chang, HC; Shung, CB; Lee, CY |
| 國立交通大學 |
2014-12-08T15:40:20Z |
A neural fuzzy resource manager for hierarchical cellular systems supporting multimedia services
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Lo, KR; Chang, CJ; Shung, CB |
| 國立交通大學 |
2014-12-08T15:27:55Z |
FAULT-TOLERANT ARCHITECTURES FOR SHARED BUFFER MEMORY SWITCH
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LIN, YF; SHUNG, CB |
| 國立交通大學 |
2014-12-08T15:27:49Z |
A HIGH SPEED REED-SOLOMON CODEC CHIP USING LOOKFORWARD ARCHITECTURE
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CHANG, JY; SHUNG, CB |
| 國立交通大學 |
2014-12-08T15:27:38Z |
Accurate logic-level power simulation using glitch filtering and estimation
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Tsai, WC; Shung, CB; Wang, DC |
| 國立交通大學 |
2014-12-08T15:27:33Z |
Queue management for shared buffer and shared multi-buffer ATM switches
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Lin, YS; Shung, CB |
| 國立交通大學 |
2014-12-08T15:27:27Z |
VLSI design of a priority arbitrator for shared buffer ATM switches
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Lin, YS; Yang, SC; Fang, SJ; Shung, CB |
| 國立交通大學 |
2014-12-08T15:27:26Z |
Reactive bandwidth arbitration for priority and multicasting control in ATM switching
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Fang, SJ; Lin, YS; Yang, SC; Shung, CB |
| 國立交通大學 |
2014-12-08T15:27:17Z |
A (208,192;8) Reed-Solomon decoder for DVD application
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Chang, HC; Shung, CB |
| 國立交通大學 |
2014-12-08T15:05:17Z |
AN INTEGRATED CAD SYSTEM FOR ALGORITHM-SPECIFIC IC DESIGN
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SHUNG, CB; JAIN, R; RIMEY, K; WANG, E; SRIVASTAVA, MB; RICHARDS, BC; LETTANG, E; AZIM, SK; THON, L; HILFINGER, PN; RABAEY, JM; BRODERSEN, RW |
| 國立交通大學 |
2014-12-08T15:05:04Z |
A 30-MHZ TRELLIS CODEC CHIP FOR PARTIAL-RESPONSE CHANNELS
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SHUNG, CB; SIEGEL, PH; THAPAR, HK; KARABED, R |
| 國立交通大學 |
2014-12-08T15:04:40Z |
GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHM
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CYPHER, R; SHUNG, CB |
| 國立交通大學 |
2014-12-08T15:04:34Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY
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SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立交通大學 |
2014-12-08T15:04:32Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
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SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立交通大學 |
2014-12-08T15:04:17Z |
REAL-TIME RECORDING RESULTS FOR A TRELLIS-CODED PARTIAL-RESPONSE (TCPR) SYSTEM
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THAPAR, HK; SHUNG, CB; RAE, JW; KARABED, R; SIEGEL, PH |
Showing items 1-25 of 31 (2 Page(s) Totally)
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