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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"su pin"的相關文件
顯示項目 56-65 / 199 (共20頁)
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| 國立交通大學 |
2017-04-21T06:50:14Z |
Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:50:10Z |
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
|
Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:50:05Z |
Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-thin-body GeOI MOSFETs
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Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:57Z |
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
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Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:47Z |
UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability
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Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:44Z |
Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its Suppression
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:30Z |
Investigation and Benchmark of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold Applications
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:09Z |
Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
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Hu, Vita Pi-Ho; Lo, Chang-Ting; Sachid, Angada B.; Su, Pin; Hu, Chenming |
顯示項目 56-65 / 199 (共20頁)
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