| 國立交通大學 |
2017-04-21T06:50:14Z |
Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET
|
Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:50:10Z |
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
|
Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:50:05Z |
Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-thin-body GeOI MOSFETs
|
Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:57Z |
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
|
Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:47Z |
UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability
|
Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:44Z |
Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its Suppression
|
Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:30Z |
Investigation and Benchmark of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs
|
Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold Applications
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:09Z |
Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
|
Hu, Vita Pi-Ho; Lo, Chang-Ting; Sachid, Angada B.; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2017-04-21T06:49:08Z |
Accurate modeling and characterization of mobility in tensile and compressive stress for state-of-the-art manufacturing NMOSFETs
|
Wang, J. -S.; Chen, William P. N.; Shih, C. -H.; Lien, C.; Su, Pin; Sheu, Y. M.; Chao, Donald Y. -S.; Goto, K. |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness
|
Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:02Z |
Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:32Z |
Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices
|
Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:17Z |
Simulation of Grain-Boundary Induced V-th Variability in Stackable NAND Flash Using a Voronoi Approach
|
Yang, Ching-Wei; Chao, Shao-Heng; Su, Pin |
| 國立交通大學 |
2016-03-28T08:17:18Z |
二維材料金氧半元件於邏輯電路與記憶體應用之適用性評估(I)
|
蘇彬; Su Pin |
| 國立交通大學 |
2016-03-28T00:04:24Z |
Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications
|
Yu, Chang-Hung; Fan, Ming-Long; Yu, Kuan-Chin; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2016-03-28T00:04:17Z |
Impact of Quantum Capacitance on Intrinsic Inversion Capacitance Characteristics and Inversion-Charge Loss for Multigate III-V-on-Insulator nMOSFETs
|
Shen, Hsin-Hung; Shen, Shih-Lun; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2015-12-02T03:00:54Z |
Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-11-26T01:07:47Z |
超薄絕緣鍺金氧半場效電晶體在量子侷限下的短通道效應模型與分析
|
謝欣原; Hsieh, Hsin-Yuan; 蘇彬; Su, Pin |
| 國立交通大學 |
2015-11-26T01:02:59Z |
Spacer之設計對多重閘極絕緣砷化銦鎵金氧半鰭狀式場效電晶體的靜電完整性及效能的影響
|
羅章庭; Lo, Chang-Ting; 蘇彬; Su, Pin |
| 國立交通大學 |
2015-11-26T00:56:23Z |
單晶三維積體之銦鎵砷/鍺超薄電晶體邏輯電路與靜態隨機存取記憶體考慮層間電耦合之分析
|
余冠瑾; Yu, Kuan-Chin; 蘇彬; Su, Pin |
| 國立交通大學 |
2015-11-26T00:55:07Z |
量子電容對於三五族多閘極金氧半場效電晶體本質反轉層電容之影響
|
沈信宏; Shen, Hsin-Hung; 蘇彬; Su, Pin |
| 國立交通大學 |
2015-07-21T11:21:14Z |
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits
|
Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T11:20:55Z |
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
|
Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:30Z |
Investigation of Backgate-Bias Dependence of Intrinsic Variability for UTB Hetero-Channel MOSFETs Considering Quantum Confinement
|
Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2015-07-21T08:31:27Z |
Evaluation of Read-and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:16Z |
Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:31:11Z |
Evaluation of Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:29:06Z |
Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation
|
Lee, Ko-Chun; Fan, Ming-Long; Su, Pin |
| 國立交通大學 |
2015-07-21T08:29:05Z |
Investigation of Multi-V-th Efficiency for Trigate GeOI p-MOSFETs Using Analytical Solution of 3-D Poisson\'s Equation
|
Wu, Shu-Hua; Yu, Chang-Hung; Chiang, Chun-Hsien; Su, Pin |
| 國立交通大學 |
2015-07-21T08:29:05Z |
Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Hsu, Chih-Wei; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2015-07-21T08:28:07Z |
Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-16T06:15:18Z |
SCHMITT TRIGGER-BASED FINFET SRAM CELL
|
Chuang Ching-Te; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:15:00Z |
INDEPENDENTY-CONTROLLED-GATE SRAM
|
CHUANG Ching-Te; Chen Yin-Nien; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:14:14Z |
Schmitt trigger-based finFET SRAM cell
|
Chuang Ching-Te; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-16T06:13:52Z |
Independently-controlled-gate SRAM
|
Chuang Ching-Te; Chen Yin-Nien; Hsieh Chien-Yu; Fan Ming-Long; Hu Pi-Ho; Su Pin |
| 國立交通大學 |
2014-12-13T10:51:54Z |
次50奈米Multiple-Gate SOI CMOS的特性分析與模式建立
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:51:33Z |
次32奈米多重閘極元件的特性分析與模式建立---變異性與微縮性，高頻類比特性，以及介觀現象的探討
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:49:45Z |
單石三維整合架構下使用前瞻元件之邏輯以及靜態隨機存取記憶體電路分析
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:49:40Z |
前瞻矽奈米元件變異性及傳輸特性綜合研究(I)
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:45:53Z |
前瞻矽奈米元件變異性及傳輸特性綜合研究(II)
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:43:14Z |
單石三維整合架構下使用前瞻元件之邏輯以及靜態隨機存取記憶體電路分析
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:42:49Z |
異質通道元件在邏輯電路及記憶體應用之適用性評估
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:41:26Z |
異質通道元件在邏輯電路及記憶體應用之適用性評估
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:41:05Z |
源/汲極串聯電阻引致對高度微縮金氧半元件汲極電流不匹配及變異之反饋效應研究
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:31:50Z |
次100奈米SOI CMOS的RF/Analog特性分析與模式建立(I)
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:31:32Z |
一個用於部分與完全解離絕緣矽電路模擬的統整元件模型---65奈米SOI CMOS基體源極內建能障降低的探討
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:30:21Z |
次100奈米SOI CMOS的RF/Analog特性分析與模式建立(II)
|
蘇彬; Su Pin |
| 國立交通大學 |
2014-12-13T10:29:57Z |
次50奈米Multiple-Gate SOI CMOS的特性分析與模式建立
|
蘇彬; Su Pin |
