|
English
|
正體中文
|
简体中文
|
Total items :0
|
|
Visitors :
51205106
Online Users :
164
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"sung tze yun"
Showing items 46-55 of 195 (20 Page(s) Totally)
<< < 1 2 3 4 5 6 7 8 9 10 > >>
View [10|25|50] records per page
| 中華大學 |
2010 |
Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2010 |
Multiplierless, Reconfigurable Folded Architecture for VLSI Wavelet Filter
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2010 |
Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2010 |
An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2010 |
A Novel Linear Array for Discrete Cosine Transform
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2010 |
Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter
|
宋志雲; Sung, Tze-Yun |
| 國立聯合大學 |
2009 |
High-SFDR and multiplierless direct digital frequency synthesizer
|
Sung, Tze-Yun; Hsin, Hsi-Chin; Ko, Lu-Ting |
| 國立聯合大學 |
2009 |
Low-power and high-SFDR direct digital frequency synthesizer based on hybrid CORDIC algorithm
|
Sung, Tze-Yun; Ko, Lyu-Ting; Hsin, Hsi-Chin |
| 國立聯合大學 |
2009 |
Quad-tree based adaptive wavelet packet image coding
|
Sung, Tze-Yun ; Hsin, Hsi-Chin |
| 國立聯合大學 |
2009 |
Reconfigurable VLSI architecture for FFT processor
|
Sung, Tze-Yun; Hsin, Hsi-Chin; Ko, Lu-Ting |
Showing items 46-55 of 195 (20 Page(s) Totally)
<< < 1 2 3 4 5 6 7 8 9 10 > >>
View [10|25|50] records per page
|
