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Showing items 21-30 of 34 (4 Page(s) Totally)
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| 國立交通大學 |
2014-12-16T06:13:48Z |
Static memory and memory cell thereof
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Jou Shyh-Jye; Tu Ming-Hsien; Hu Yu-Hao; Chuang Ching-Te; Chiu Yi-Wei |
| 國立交通大學 |
2014-12-16T06:13:47Z |
Static random access memory apparatus and bit-line voltage controller thereof
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Chuang Ching-Te; Lien Nan-Chun; Liao Wei-Nan; Chang Chi-Hsin; Yang Hao-I; Hwang Wei; Tu Ming-Hsien |
| 國立交通大學 |
2014-12-12T01:24:38Z |
超低功耗次臨界操作靜態隨機存取記憶體的設計與實現
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杜明賢; Tu, Ming-Hsien; 周世傑; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:46:21Z |
A reconfigurable MAC architecture implemented with mixed-V(t) standard cell library
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Wang, Li-Rong; Chiu, Yi-Wei; Hu, Chia-Lin; Tu, Ming-Hsien; Jou, Shyh-Jye; Lee, Chung-Len |
| 國立交通大學 |
2014-12-08T15:36:49Z |
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
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Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Chu, Yuan-Hua; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:13Z |
A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
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Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:45Z |
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
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Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang |
| 國立交通大學 |
2014-12-08T15:32:50Z |
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design
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Wang, Li-Rong; Tu, Ming-Hsien; Jou, Shyh-Jye; Lee, Chung-Len |
| 國立交通大學 |
2014-12-08T15:30:07Z |
Testing Strategies for a 9T Sub-threshold SRAM
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Yang, Hao-Yu; Lin, Chen-Wei; Chen, Hung-Hsin; Chao, Mango C. -T.; Tu, Ming-Hsien; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
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Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
Showing items 21-30 of 34 (4 Page(s) Totally)
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