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Institution Date Title Author
國立交通大學 2014-12-08T15:48:47Z A logical fault model for library coherence checking Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:42:37Z On automatic-verification pattern generation for SoC with port-order fault model Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:41:53Z An automorphic approach to verification pattern generation for SoC design verification using port-order fault model Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:41:36Z Automatic interconnection rectification for SoC design verification based on the port order fault model Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:26:53Z On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:26:47Z An improved AVPG algorithm for SoC design verification using port order fault model Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:26:15Z SOC design integration by using automatic interconnection rectification Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:26:11Z An automatic interconnection rectification technique for SoC design integration Wang, CY; Tung, SW; Jou, JY

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