| 淡江大學 |
2008-07 |
A New Low Power, High Speed Double-Edge Triggered Flip-Flop
|
Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung |
| 淡江大學 |
2008-04-16 |
A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
|
Cheng, Kuo-hsing; Hung, Cheng-liang; Chang, Chih-hsien; Lo, Yu-lung; Yang, Wei-bin; Miaw, Jiunn-way |
| 淡江大學 |
2007-04 |
A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
|
Cheng, Kuo-Hsing; Chen, Chao-An; Yang, Wei-Bin; Cho, Feng-Hsin |
| 淡江大學 |
2006-12 |
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
|
Jau, Ting-sheng; Yang, Wei-bin; Lo, Yu-lung |
| 淡江大學 |
2006-12 |
Analysis and Design of High Performance, Low Power Multiple Ports
|
Jau, Ting-sheng; Yang, Wei-bin; Chang, Chung-yu |
| 淡江大學 |
2006-05 |
The new improved pseudo fractional-N clock generator with 50% duty cycle
|
Kuo, Shu-chang; Hung, Tzu-chien; Yang, Wei-bin |
| 淡江大學 |
2005-09-23 |
Programmable fractional-N clock generators
|
郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
| 淡江大學 |
2005-08-29 |
The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle
|
Yang, Wei-bin; Kuo, Shu-chang; Chu, Yuan-hua; Cheng, Kuo-hsing |
| 淡江大學 |
2004-05 |
A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
|
Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
| 淡江大學 |
2003-11 |
A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
|
Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
| 淡江大學 |
2001-09 |
A difference detector PFD for low jitter PLL
|
鄭國興; Cheng, Kuo-hsing; Yao, Tse-hua; Jiang, Shu-yu; Yang, Wei-bin |
| 淡江大學 |
2001-05-06 |
A low-power high driving ability voltage control oscillator used in PLL
|
鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Chung, Chun-fu |
| 淡江大學 |
1999-09-05 |
The suggestion for CFS CMOS buffer
|
Cheng, Kuo-hsing; Yang, Wei-bin |
| 淡江大學 |
1999-08 |
A Low-Power CMOS Output Buffer
|
Cheng, Kuo-Hsing; Yang, Wei-Bin |
| 淡江大學 |
1999-03 |
The charge-transfer feedback-controlled split-path CMOS buffer
|
Cheng, Kuo-hsing; Yang, Wei-bin; Huang, Hong-yi |
| 淡江大學 |
1997-11-29 |
Low-voltage-swing low-power CMOS buffer
|
鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin |
| 淡江大學 |
1997-08-21 |
A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process
|
鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Laiw, Yii-yih |
| 淡江大學 |
1997-08 |
The Charge-Transfer Feedback-Controlled Split-Path CMOS Buffer
|
Cheng, Kuo-Hsing; Yang, Wei-Bin; Huang, Hong-Yi |
| 淡江大學 |
1997-08 |
A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
|
Cheng, Kuo-Hsing; Yee, Liow Yu; Liaw, Yii-Yih; Yang, Wei-Bin |
