| 國立交通大學 |
2018-08-21T05:56:49Z |
ESD Protection Design for High-Speed Applications in CMOS Technology
|
Chen, Jie-Ting; Lin, Chun-Yu; Chang, Rong-Kun; Ker, Ming-Dou; Tzeng, Tzu-Chien; Lin, Tzu-Chiang |
| 國立交通大學 |
2014-12-08T15:18:07Z |
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
|
Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:36:14Z |
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
|
Ker, MD; Hsu, HC |
| 國立交通大學 |
2014-12-08T15:26:34Z |
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
|
Ker, MD; Chuang, CH; Hsu, KC; Lo, WY |
| 國立交通大學 |
2014-12-08T15:25:20Z |
ESD protection design for mixed-voltage I/O interfaces - Overview
|
Ker, Ming-Dou; Lin, Kun-Hsien |
| 國立交通大學 |
2014-12-08T15:26:14Z |
ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique
|
Ker, MD; Hsu, HC |
| 國立交通大學 |
2015-07-21T08:31:29Z |
ESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technology
|
Lin, Chun-Yu; Chu, Li-Wei; Tsai, Shiang-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Wei, Yu-Lin; Chang, Tzu-Heng |
| 國立交通大學 |
2017-04-21T06:56:36Z |
ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
|
Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi |
| 國立交通大學 |
2017-04-21T06:48:45Z |
ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
|
Chu, Li-Wei; Lin, Chun-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Tseng, Jen-Chou; Jou, Chewn-Pu; Tsai, Ming-Hsien |
| 國立交通大學 |
2019-10-05T00:09:47Z |
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications
|
Hung, Tao-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:18:35Z |
ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
|
Ker, MD; Chang, WJ |
| 國立交通大學 |
2014-12-08T15:44:57Z |
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
|
Ker, MD; Chen, TY; Wu, CY; Chang, HH |
| 國立交通大學 |
2018-08-21T05:57:09Z |
ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process
|
Hung, Tao-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:38:36Z |
ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins
|
Ker, MD; Chang, CY; Chang, YS |
| 國立交通大學 |
2014-12-08T15:26:36Z |
ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins
|
Ker, MD; Chang, CY; Chang, YS |
| 國立交通大學 |
2019-08-02T02:18:28Z |
ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains
|
Chen, Jie-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:12Z |
ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
|
Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2014-12-08T15:38:25Z |
ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 義守大學 |
2010-12 |
ESD Protection Design with Lateral DMOS Transistor in 40-V BCD Technology
|
Chang-Tzu Wang;Ming-Dou Ker |
| 國立交通大學 |
2019-04-02T06:04:53Z |
ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications
|
Ker, Ming-Don; Lin, Chun-Yu; Wu, Yi-Han; Wang, Wen-Tai |
| 國立交通大學 |
2014-12-08T15:11:24Z |
ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
|
Ker, Ming-Dou; Chang, Wei-Jen |
| 國立交通大學 |
2017-04-21T06:55:35Z |
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:10Z |
ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:26:55Z |
ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design
|
Chen, TY; Ker, MD |
| 國立交通大學 |
2014-12-16T06:15:12Z |
ESD PROTECTION STRUCTURE FOR 3D IC
|
Chen Kuan-Neng; Lai Ming-Fang; Chen Hung-Ming |
