| 國立臺灣科技大學 |
2010 |
A 0.18 mu m CMOS Quadrature VCO Using the Quadruple Push-Push Technique
|
Jang, S.L.;Shih, C.C.;Liu, C.C.;Juang, M.H. |
| 國立臺灣科技大學 |
2011 |
A 0.18 mu m CMOS Wide-Band Injection-Locked Frequency Divider Using Push-Push Oscillator
|
Jang, S.L.;Chang, C.W.;Chen, Y.S.;Huang, J.F.;Hsieh, J.W.;Huang, C.W. |
| 臺大學術典藏 |
2018-09-10T09:25:23Z |
A 0.18 um CMOS self-mixing frequency tripler
|
Y.-T. Lo;J.-F. Kiang; Y.-T. Lo; J.-F. Kiang; JEAN-FU KIANG |
| 國立中山大學 |
2006-04 |
A 0.18 µm CMOS prototype of COFDM demodulator for European DVB-T standard
|
C.C. Wang;J.M. Huang;Y.M. Tseng;C.Y. Chang |
| 國立交通大學 |
2014-12-08T15:19:20Z |
A 0.18-mu m CMOS CMFB downconversion micromixer with deep N-well technology for LO-RF and LO-IF isolation improvements
|
Meng, CC; Hsu, SK; Wu, TH; Huang, GW |
| 臺大學術典藏 |
2018-09-10T09:43:53Z |
A 0.18-μ m CMOS Dual-band frequency synthesizer with spur reduction calibration
|
Chen, Y.-W.;Yu, Y.-H.;Chen, Y.-J.E.; Chen, Y.-W.; Yu, Y.-H.; Chen, Y.-J.E.; YI-JAN EMERY CHEN |
| 國立臺灣大學 |
2008 |
A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier
|
Wang, I-Hsin; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T08:14:43Z |
A 0.18-μm CMOS RF transceiver with self-detection and calibration functions for bluetooth V2.1 + EDR applications
|
Hu, W.-Y.;Lin, J.-W.;Tien, K.-C.;Hsieh, Y.-H.;Chen, C.-L.;Tso, H.-T.;Shih, Y.-S.;Hu, S.-C.;Chen, S.-J.; Hu, W.-Y.; Lin, J.-W.; Tien, K.-C.; Hsieh, Y.-H.; Chen, C.-L.; Tso, H.-T.; Shih, Y.-S.; Hu, S.-C.; Chen, S.-J.; SAO-JIE CHEN |
| 國立高雄師範大學 |
2006-08 |
A 0.18-μm CMOS UWB Low Noise Amplifier for 3.1-7.4GHz
|
Ruey-Lue Wang;Hsiang-Chen Kuo;Shih-Chih Chen; 王瑞祿 |
| 國立高雄師範大學 |
2006-12 |
A 0.18-μm CMOS UWB Low Noise Amplifier for Full-Band(3.1-10.6GHZ) Application
|
Ruey-Lue Wang;Shih-Chih Chen;Hsiang-Chen Kuo;Chien-Hsuan Liu; 王瑞祿 |
| 國立臺灣科技大學 |
2012 |
A 0.18-μm SiGe BiCMOS HBT VCO using diode degeneration
|
Jang, S.-L.;Hsieh, C.-W.;Chang, C.-W.;Hsue, C.-W. |
| 國立交通大學 |
2019-04-02T06:04:26Z |
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications
|
Hong, Hao-Chiao; Chiu, Yi |
| 國立臺灣科技大學 |
2009-09 |
A 0.22 V Quadrature VCO in 90 nm CMOS Process
|
Sheng-Lyang Jang;Chuang-Jen Huang;Cheng-Chen Liu;Ching-Wen Hsue |
| 國立交通大學 |
2014-12-08T15:08:26Z |
A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
|
Wong, Cheng-Chi; Tang, Cheng-Hao; Lai, Ming-Wei; Zheng, Yan-Xiu; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen-Yi; Su, Yu-T. |
| 國立成功大學 |
2003-02 |
A 0.25-mu m 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer
|
Yen, Cheng-Chi; Chuang, Huey-Ru |
| 臺大學術典藏 |
2018-09-10T09:25:34Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
|
T.-T. Liu;J. Rabaey; T.-T. Liu; J. Rabaey; TSUNG-TE LIU |
| 臺大學術典藏 |
2018-09-10T09:50:56Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
|
Liu, T.-T.;Rabaey, J.M.; Liu, T.-T.; Rabaey, J.M.; TSUNG-TE LIU |
| 臺大學術典藏 |
2019-10-31T07:12:33Z |
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
|
HSIN-SHU CHEN;Wen-Jong Wu;Micka?l Lallart;Hsin-Shu Chen;Kai-Ren Cheng; Kai-Ren Cheng; Hsin-Shu Chen; Micka?l Lallart; Wen-Jong Wu; HSIN-SHU CHEN |
| 臺大學術典藏 |
2020-01-17T07:48:26Z |
A 0.25�gm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
|
WEN-JONG WU;Wu, W.-J.;Lallart, M.;Chen, H.-S.;Cheng, K.-R.; Cheng, K.-R.; Chen, H.-S.; Lallart, M.; Wu, W.-J.; WEN-JONG WU |
| 國立臺灣科技大學 |
2010-03 |
A 0.3 V Cross-Coupled VCO Using Dynamic Threshold MOSFET
|
Sheng-Lyang Jang;Chuang-Jen Huang;Ching-Wen Hsue;Chia-Wei Chang |
| 朝陽科技大學 |
2021-10-02 |
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications
|
Lin,Jin-Fa; Tsai, Chang-Ming; Tsai, Ming-Yan; Hsia, Shih-Chang; Morsalin, S. M. Salahuddin; Sheu, Ming-Hwa; 林進發 |
| 國立臺灣大學 |
2004 |
A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-μm CMOS technology
|
Tsai, Ming-Da; Wang, Huei |
| 臺大學術典藏 |
2020-06-11T06:16:48Z |
A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator
|
Chang, C.-K.;Tsai, Y.-K.;Cheng, K.-H.;Lu, L.-H.; Chang, C.-K.; Tsai, Y.-K.; Cheng, K.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 國立交通大學 |
2015-07-21T08:29:40Z |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
|
Lu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin |
| 臺大學術典藏 |
2020-06-11T06:31:42Z |
A 0.33 V 683 μW K-band transformer-based receiver front-end in 65 nm CMOS technology
|
Cheng, J.-H.;Hsieh, C.-L.;Wu, M.-H.;Tsai, J.-H.;Huang, T.-W.; Cheng, J.-H.; Hsieh, C.-L.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
|
Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立臺灣科技大學 |
2010 |
A 0.35 mu m CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage-current feedback topology
|
Jang, S.L.;Liu, C.C.;Yang, R.K.;Shih, C.C.;Chang, C.W.;Yeh, H.A. |
| 國立交通大學 |
2017-04-21T06:55:34Z |
A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
|
Wu, Shang-Lin; Lu, Chien-Yu; Tu, Ming-Hsien; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te |
| 國立臺灣科技大學 |
2011 |
A 0.35-mu m CMOS CROSS-COUPLED COMPLEMENTARY COLPITTS VOLTAGE CONTROLLED OSCILLATOR
|
Jang, S.L.;Liu, W.C.;Chang, C.W.;Huang, J.F. |
| 國立臺灣科技大學 |
2010 |
A 0.35-mu m CMOS DIVIDE-BY-3 LC INJECTION-LOCKED FREQUENCY DIVIDER USING LINEAR MIXERS
|
Jang, S.L.;Chen, H.S.;Liu, C.C.;Juang, M.H. |
| 國立臺灣科技大學 |
2011 |
A 0.35-mu m CMOS FREQUENCY DIVIDER IMPLEMENTED WITH THE WAFFLE INJECTION MOSFET
|
Jang, S.L.;Cheng, C.L.;Chang, C.W.;Juang, M.H. |
| 國立臺灣科技大學 |
2008-04 |
A 0.35-um CMOS switched-inductor dual-band LC-tank frequency divider
|
Sheng-Lyang Jang;Che Yi Lin;Chien-Feng Lee |
| 國立臺灣科技大學 |
2008 |
A 0.35-um CMOS switched-inductor dual-band LC-tank frequency divider
|
Jang S.-L.; Che Y.L.; Lee C.-F. |
| 國立交通大學 |
2020-02-02T23:54:35Z |
A 0.35-V 240-W Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications
|
Wang, Shih-Hsing; Hung, Chung-Chih |
| 國立臺灣科技大學 |
2009-04 |
A 0.35?m CMOS divide-by-3 LC injection-locked frequency divider
|
Sheng-Lyang Jang;Chuang-Jen Huang;Cheng-Chen Liu |
| 元智大學 |
2016-08-02 |
A 0.35V, 500Mbps Digitalized LVDS driver in 0.18m CMOS technology
|
Shi-Fung Zhou; Hungwen Lin |
| 國立臺灣科技大學 |
2009 |
A 0.35弮m CMOS divide-by-3 LC injection-locked frequency divider
|
Jang S.-L.; Huang C.-J.; Liu C.-C. |
| 臺大學術典藏 |
2019-10-24T07:27:59Z |
A 0.38-V, sub-mW 5-GHz low noise amplifier with 43.6% bandwidth for next generation radio astronomical receivers in 90-nm CMOS
|
王暉;HUEI WANG;Huei Wang;Yu-Hsuan Lin;Chau-Ching Chiong;Ying Chen; Ying Chen; Chau-Ching Chiong; Yu-Hsuan Lin; Huei Wang; HUEI WANG; 王暉 |
| 國立交通大學 |
2020-07-01T05:22:04Z |
A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications
|
Wang, Shih-Hsing; Hung, Chung-Chih |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS
|
Hsieh, C.-E.;Liu, S.-I.; Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU |
| 淡江大學 |
2012-07-15 |
A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS
|
Yang, Wei-Bin |
| 元智大學 |
2020/7/28 |
A 0.3V, 625Mbps LVDS Driver in 0.18um CMOS Technology
|
Hungwen Lin; Tzu-Hao Lin |
| 臺大學術典藏 |
2018-09-10T08:15:03Z |
A 0.4-6 GHz variable-gain driver amplifier for software-defined radio
|
Lin, K.-T.; Chen, H.-K.; Wang, T.; Lu, S.-S.; SHEY-SHI LU |
| 國立成功大學 |
2022 |
A 0.4-mA-Quiescent-Current, 0.00091%-THD+N Class-D Audio Amplifier With Low-Complexity Frequency Equalization for PWM-Residual- Aliasing Reduction
|
Qiu, Y.-Z.;Chien, S.-H.;Kuo, T.-H. |
| 國立成功大學 |
2022-02 |
A 0.4-mA-Quiescent-Current, 0.00091%-THD+N Class-D Audio Amplifier With Low-Complexity Frequency Equalization for PWM-Residual-Aliasing Reduction
|
Qiu;Yi-Zhi;Chien;Shih-Hsiung;Kuo;Tai-Haur |
| 國立成功大學 |
2020 |
A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction
|
Chien, S.-H.;Kuo, T.-H.;Huang, Huang H.-Y.;Wang, H.-B.;Qiu, Y.-Z. |
| 國立交通大學 |
2017-04-21T06:48:47Z |
A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOC
|
Dhong, Sang; Guo, Richard; Kuo, Ming-Zhang; Yang, Ping-Lin; Lin, Cheng-Chung; Huang, Kevin; Wang, Min-Jer; Hwang, Wei |
| 臺大學術典藏 |
2020-06-11T06:34:47Z |
A 0.43pJ/bit true random number generator
|
Kuan, T.-K.;Chiang, Y.-H.;Liu, S.-I.; Kuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立交通大學 |
2016-03-28T00:05:45Z |
A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
|
Lin, Tay-Jyi; Chien, Cheng-An; Chang, Pei-Yao; Chen, Ching-Wen; Wang, Po-Hao; Shyu, Ting-Yu; Chou, Chien-Yung; Luo, Shien-Chun; Guo, Jiun-In; Chen, Tien-Fu; Chuang, Gene C. H.; Chu, Yuan-Hua; Cheng, Liang-Chia; Su, Hong-Men; Jou, Chewnpu; Ieong, Meikei; Wu, Cheng-Wen; Wang, Jinn-Shyan |
| 國立交通大學 |
2018-08-21T05:56:39Z |
A 0.4V 53dB SNDR 250 MS/s Time-Based CT Delta Sigma Analog to Digital Converter
|
Chen, Hung-Kai; Chen, Wei-Zen; Ren Zhiyuan |
