| 國立交通大學 |
2014-12-08T15:32:53Z |
A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique
|
Li, Chun-Hsing; Liu, Yen-Lin; Kuo, Chien-Nan |
| 國立交通大學 |
2014-12-08T15:22:05Z |
A 0.6-V 30 GHz CMOS Quadrature VCO Using Microwave 1:1:1 Trifilar Transformer
|
Syu, Jin-Siang; Lu, Hsi-Liang; Meng, Chinchun |
| 臺大學術典藏 |
2020-06-11T06:31:43Z |
A 0.6-V 336-μW 5-GHz LNA using a low-voltage and gain-enhancement architecture
|
Hsieh, C.-L.;Wu, M.-H.;Cheng, J.-H.;Tsai, J.-H.;Huang, T.-W.; Hsieh, C.-L.; Wu, M.-H.; Cheng, J.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 臺大學術典藏 |
2020-06-11T06:16:54Z |
A 0.6-V delta-sigma ADC wih 57-dB dynamic range
|
Wei, C.-H.;Lu, L.-H.; Wei, C.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 臺大學術典藏 |
2018-09-10T08:19:08Z |
A 0.6-V delta-sigma ADC with 57-dB dynamic range
|
C.-H. Wei;L.-H. Lu; C.-H. Wei; L.-H. Lu; LIANG-HUNG LU |
| 國立臺灣科技大學 |
2010 |
A 0.6-V LOW-POWER ARMSTRONG VCO IN 0.18 mu M CMOS
|
Liu, C.C.;Jang, S.L.;Chen, J.J.;Juang, M.H. |
| 臺大學術典藏 |
2019-10-31T07:12:34Z |
A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System
|
HSIN-SHU CHEN;Hsin-Shu Chen;Li-Yu Huang;Yao-Sheng Hu; Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen; HSIN-SHU CHEN |
| 國立交通大學 |
2014-12-08T15:20:29Z |
A 0.6V 200kHz Silicon Oscillator with Temperature Compensation for Wireless Sensing Applications
|
Yu, Chien-Ying; Lee, Chen Yi |
| 臺大學術典藏 |
2018-09-10T15:22:47Z |
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS
|
Hu, Y.-S.;Shih, C.-H.;Tai, H.-Y.;Chen, H.-W.;Chen, H.-S.; Hu, Y.-S.; Shih, C.-H.; Tai, H.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立臺灣大學 |
2007 |
A 0.6V Low Power UWB CMOS LNA
|
Yu, Yueh-Hua; Chen, Y.-J.E.; Heo, D. |
| 國立臺灣大學 |
2007-03 |
A 0.6V Low Power UWB CMOS LNA
|
Yu, Yueh-Hua; Chen, Yi-Jan Emery; Heo, Deukhyoun |
| 國立交通大學 |
2017-04-21T06:48:28Z |
A 0.6V, 1.3GHZ DYNAMIC COMPARATOR WITH CROSS-COUPLED LATCHES
|
Kuo, Bo-Jyun; Chen, Bo-Wei; Tsai, Chia-Ming |
| 國立交通大學 |
2014-12-08T15:12:44Z |
A 0.7 V transformer-feedback CMOS low-noise amplifier for 5-GHz wireless LAN
|
Wu, H. I.; Fan, R. S.; Jou, C. F. |
| 臺大學術典藏 |
2018-09-10T07:42:57Z |
A 0.7-V 60-GHz Low-Power LNA with Forward Body Bias Technique in 90 nm CMOS Process
|
Wei-Heng Lin; Jeng-Han Tsai; Yung-Nien Jen; Tian-Wei Huang; Huei Wang; TIAN-WEI HUANG; Wei-Heng Lin;Jeng-Han Tsai;Yung-Nien Jen;Tian-Wei Huang;Huei Wang |
| 臺大學術典藏 |
2020-06-04T07:53:46Z |
A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process
|
Lin, W.-H.;Tsai, J.-H.;Jen, Y.-N.;Huang, T.-W.;Wang, H.; Lin, W.-H.; Tsai, J.-H.; Jen, Y.-N.; Huang, T.-W.; Wang, H.; HUEI WANG |
| 國立高雄師範大學 |
2012-12 |
A 0.7-V Input Output-capacitor-free Digitally Controlled Low-dropout Regulator with High Current Efficiency in 0.35-?m CMOS Technology
|
Yu-Lung Lo;Wei-Jen Chen; 羅有龍 |
| 國立交通大學 |
2014-12-08T15:12:45Z |
A 0.75 VCMOS low-noise amplifier for ultra wide-band wireless receiver
|
Wu, Hui-I.; Hsiung, Zi Hao; Jou, Christina F. |
| 國立交通大學 |
2014-12-08T15:34:48Z |
A 0.75-2.67 GHz 5-bit Vector-Sum Phase Shifter
|
Yan, Tzu-Chao; Lin, Wei-Zhen; Kuo, Chien-Nan |
| 國立東華大學 |
2007-09 |
A 0.7V 3-5GHz CMOS Low Noise Amplifier for Ultra-wideband Applications
|
翁若敏; Weng, Ro-Min; Hsiao, Chih-Lung ; Lee, Wei-Chi |
| 國立高雄師範大學 |
2008-06 |
A 0.7V Low-Voltage Folded-Cascode Uwblana with a Resistive Feedback
|
Ruey-Lue Wang;Cheng-Lin Huang;Shih-Chih Chen;Jui-Hao Shang;Cheng-Lung Tsai; 王瑞祿 |
| 國立臺灣大學 |
2006 |
A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop
|
Chang, Hsiang-Hui; Chang, Jung-Yu; Kuo, Chun-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-12 |
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI
|
Chen, H.P.; Kuo, J.B. |
| 臺大學術典藏 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 臺大學術典藏 |
2004-09 |
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator
|
Liu, Tsung-Te; Wang, Chorng-Kuang; Liu, Tsung-Te; Wang, Chorng-Kuang |
