| 南台科技大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
Chua-Chin Wang; Yih-Long Tseng; 李博明; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Hunng; 王朝欽 |
| 南台科技大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
Chua-Chin Wang; Yih-Long Tseng; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Huang |
| 國立中山大學 |
2003 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
C.C. Wang;Y.L. Tseng;P.M. Lee;R.C. Lee;C.J. Huang |
| 國立中山大學 |
2003-09 |
A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic
|
C.C. Wang; Y.L. Tseng; P.M. Lee; R.C. Lee; C.J. Huang |
| 南台科技大學 |
2000-12 |
A 1.25 GHz 8-bit Tree-Structured Carry Lookahead Adder
|
Chua-Chin Wang; Po-Ming Lee; Chenn-Jung Huang; Rong-Chin Lee |
| 國立中山大學 |
2000-12 |
A 1.25 GHz 8-bit tree-structured carry lookahead adder
|
C.C. Wang;P.M. Lee;C.J. Huang;R.C. Lee |
| 國立臺灣科技大學 |
2008 |
A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition
|
Oulee C.-S.; Yang R.-J. |
| 臺大學術典藏 |
2018-09-10T08:18:16Z |
A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression
|
Chao-Ching Hung;I-Fong Chen;Shen-Iuan Liu; Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU |
| 國立中山大學 |
2003-08 |
A 1.26ns access time current-mode sense amplifier design for SRAMs
|
C.C. Wang;Y.L. Tseng;C.C. Li;R. Hu |
| 元智大學 |
2015-08-04 |
A 1.2V 3.5Gbps Digitalized LVDS driver in 0.18um CMOS technology
|
Jhih-Siang Shao; Shi-Fung Zhou; Hungwen Lin |
