| 國立交通大學 |
2014-12-08T15:11:24Z |
ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
|
Ker, Ming-Dou; Chang, Wei-Jen |
| 國立交通大學 |
2017-04-21T06:55:35Z |
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:10Z |
ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:26:55Z |
ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design
|
Chen, TY; Ker, MD |
| 國立交通大學 |
2014-12-16T06:15:12Z |
ESD PROTECTION STRUCTURE FOR 3D IC
|
Chen Kuan-Neng; Lai Ming-Fang; Chen Hung-Ming |
| 國立交通大學 |
2014-12-08T15:25:32Z |
ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications
|
Ker, MD; Chang, WJ; Yang, M; Chen, CC; Chan, MC; Shieh, WT; Yen, KL |
| 國立交通大學 |
2014-12-08T15:28:05Z |
ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process
|
Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Chang, Tzu-Heng |
| 國立交通大學 |
2014-12-08T15:43:41Z |
ESD protection under grounded-up bond pads in 0.13 mu m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology
|
Chou, KY; Chen, MJ |
| 大葉大學 |
2000 |
ESD robustness designs of power MOSFET ICs
|
陳勝利 |
| 大葉大學 |
2000-11 |
ESD Robustness Designs of Power MOSFET ICs
|
陳勝利 |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD robustness of thin-film devices with different layout structures in LTPS technology
|
Deng, Chih-Kang; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:48:20Z |
ESD Self-Protection Design on 2.4-GHz T/R Switch for RF Application in CMOS Process
|
Lin, Chun-Yu; Liu, Rui-Hong; Ker, Ming-Dou |
| 亞洲大學 |
2010-10 |
ESD Simulation on GGNMOS for 40V BCD
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 國立交通大學 |
2014-12-08T15:26:50Z |
ESD test methods on integrated circuits: An overview
|
Ker, MD; Peng, JH; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:23:05Z |
ESD-Aware Circuit Design in CMOS Integrated Circuits to Meet System-Level ESD Specification in Microelectronic Systems
|
Ker, Ming-Dou |
| 國立交通大學 |
2018-08-21T05:57:09Z |
ESD-Induced Latchup-Like Failure in a Touch Panel Control IC
|
Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
|
Ker, Ming-Dou; Hsiao, Yuan-Wen; Wu, Woei-Lin |
| 大葉大學 |
2007-01-26 |
ESD/TLP量測儀器及電子元件抗ESD分析研究
|
王光一, 陳勝利 許崇宜 |
| 中國文化大學 |
2006-06-30 |
ESD靜電防護材料之製備及其抗靜電性質之研究
|
邢文灝; 莊佾宸 |
| 臺大學術典藏 |
1989-09 |
ESEMAP:An Expert System for Emergency Management of Air Pollution
|
Wang, J. C.; Huang, Han-Pang; Li, Chang-Sheng; 黃漢邦; Wang, J. C.; 李常聲; Huang, Han-Pang; Li, Chang-Sheng |
| 國立臺灣大學 |
1990 |
ESEMAP:An Expert System for Emergency Management of Air Pollution
|
梁文傑; 黃孝平; Wang, J. C.; Liang, Wen-Jey; Huang, Hsiao-Ping; Wang, J. C. |
| 國立臺灣大學 |
1989-09 |
ESEMAP:An Expert System for Emergency Management of Air Pollution
|
黃漢邦; Wang, J. C.; 李常聲; Huang, Han-Pang; Wang, J. C.; Li, Chang-Sheng |
| 國立交通大學 |
2018-08-21T05:52:55Z |
eSES: Enhanced Simple Energy Saving for LTE HeNBs
|
Lin, Yi-Bing; Wang, Li-Chang; Chen, Wei-Cheng |
| 國立臺灣科技大學 |
2014 |
ESFM: An Essential Software Framework for Meshfree Methods
|
Hsieh, Y.-M.;Pan, M.-S. |
| 淡江大學 |
2023-04-18 |
ESG Effects on Stock Prices During the Epidemic: Empirical Investigations for the Finance Holding Companies in Taiwan
|
Lin, Yen-ling |
