| 臺大學術典藏 |
2020-06-11T06:31:42Z |
A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process
|
Jen, Y.-N.;Tsai, J.-H.;Peng, C.-T.;Huang, T.-W.; Jen, Y.-N.; Tsai, J.-H.; Peng, C.-T.; Huang, T.-W.; TIAN-WEI HUANG |
| 元智大學 |
2009-01 |
A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-µm CMOS process
|
蔡政翰; Yung-Nien Jen; Chung-Te Peng; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:44Z |
A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process
|
Yung-Nien Jen; Jeng-Han Tsai; Chung-Te Peng; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:44Z |
A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process
|
Yung-Nien Jen; Jeng-Han Tsai; Chung-Te Peng; Tian-Wei Huang |
| 淡江大學 |
2005-03 |
A 20 Years Overview and Prospect of Interpretive Research in Taiwan: 1984-2003
|
陳維立; Wu, H. C.; Chen, W. J. |
| 臺大學術典藏 |
2021-09-02T00:05:04Z |
A 20-43 GHz Low Noise GaAs Downconverter with Gbps Data-Links for Full 5G K/Ka-Band Backhauls
|
Chen C.-N;Kuo T.-Y;Wang H.; Chen C.-N; Kuo T.-Y; Wang H.; HUEI WANG |
| 臺大學術典藏 |
2021-03-12T08:41:03Z |
A 20-Gb/s 1: 2 demultiplexer with capacitive-splitting current-mode-logic latches
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 國立臺灣大學 |
2007 |
A 20-Gb/s 1:2 Demultiplexer with capacitive-splitting current-mode-logic latches
|
Chien, Jun-Chau; Lu, Liang-Hung |
| 國立臺灣大學 |
2005-06 |
A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-/spl mu/m CMOS technology
|
Lee, Jri; Ding, Jian-Yu; Cheng, Tuan-Yi |
| 臺大學術典藏 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri; Lee, Jri |
| 國立臺灣大學 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
|
Jri Lee; JRI LEE |
| 國立臺灣大學 |
2006 |
A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology
|
Lee, Jri |
| 國立臺灣大學 |
2008 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, Mingchung |
| 國立臺灣大學 |
2008-03 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, M. |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
|
Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 國立交通大學 |
2014-12-08T15:34:51Z |
A 20-Gb/s Optical Receiver with Integrated Photo Detector in 40-nm CMOS
|
Huang, Shih-Hao; Chen, Wei-Zen |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology
|
Kao, S.-Y.;Liu, S.-I.; Kao, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立交通大學 |
2019-04-02T06:04:28Z |
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery
|
Lee, Yuan-Sheng; Chen, Wei-Zen |
| 國立彰化師範大學 |
2005-02 |
A 20-GHz CMOS RF Down-Conversion with an On-chip Antenna
|
Su, Yu; Lin, Jau-Jr; Kenneth, K. O. |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator
|
Y-H Kang;C-Y Lin;T-C Lee; Y-H Kang; C-Y Lin; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:20:57Z |
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator.
|
Kang, Yu-Hsuan;Lin, Chin-Yu;Lee, Tai-Cheng; Kang, Yu-Hsuan; Lin, Chin-Yu; Lee, Tai-Cheng; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-MHz to 3-GHz wide-range multiphase delay-locked loop
|
Chuang, C.-N.;Liu, S.-I.; Chuang, C.-N.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立中山大學 |
2002 |
A 20-year record of Sr-90 and heavy metals off the third Nuclear Power Plant in southern Taiwan
|
C.T.A. Chen;S.J. Jiang |
| 中國醫藥大學 |
2012-03 |
A 20-year retained guidewire, should it be removed?
|
林晏年(Yen-Nien Lin);周仁偉(Jen-Wei Chou);陳瑩惠(Yin-Huie Chen);劉健佑(Jian-You Liu);何承懋(Cheng-Mao Ho)* |
