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"許健"
Showing items 81-90 of 107 (11 Page(s) Totally)
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| 亞洲大學 |
2010-11 |
An 800 Volts High Voltage Interconnection Level Shifter Using Floating Poly Field Plate (FPFP) Method
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-10 |
ESD Simulation on GGNMOS for 40V BCD
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-07 |
An Analytical Model of Surface Electric Field Distributionsin in Ultrahigh-Voltage Metal–Oxide–Semiconductor Devices
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-07 |
An Analytical Model of Surface Electric Field Distributions in Ultrahigh-Voltage Buried P-top Lateral Diffused Metal-Oxide-Semiconductor Devices
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;張怡楓;Chang, Yi-Fong;曹世昌;Tsaur, Shyh-Chang |
| 亞洲大學 |
2010-03 |
Combining 2D and 3D Device Simulations for Optimizing LDMOS Design
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-03 |
Reduction of Kink Effect in SOI LDMOS Structure with Linear Drift Region Thickness
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-03 |
Comparison of High Voltage (200-300 Volts) Lateral Power MOSFETs for Power Integrated Circuits
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;陳兆南 |
| 亞洲大學 |
2010 |
A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques
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郭宇?;GUO, Yu-Feng;王志功;WANG, Zhi-Gong;許健;Sheu, Gene |
| 亞洲大學 |
2009.08 |
Dependence of Breakdown Voltage on Drift Length and Linear Doping Gradients in SOI RESURF LDMOS Devices
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2009.07 |
VARIATION OF LATERAL THICKNESSTECHNIQUES IN SOI LATERAL HIGH VOLTAGE DEVICE
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郭宇鋒;Guo, Yufeng;王至剛;Wang1, Zhigong;許健;Sheu, Gene |
Showing items 81-90 of 107 (11 Page(s) Totally)
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