|
English
|
正體中文
|
简体中文
|
总笔数 :0
|
|
造访人次 :
53274350
在线人数 :
616
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"許健"的相关文件
显示项目 81-90 / 107 (共11页)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
每页显示[10|25|50]项目
| 亞洲大學 |
2010-11 |
An 800 Volts High Voltage Interconnection Level Shifter Using Floating Poly Field Plate (FPFP) Method
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-10 |
ESD Simulation on GGNMOS for 40V BCD
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-07 |
An Analytical Model of Surface Electric Field Distributionsin in Ultrahigh-Voltage Metal–Oxide–Semiconductor Devices
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-07 |
An Analytical Model of Surface Electric Field Distributions in Ultrahigh-Voltage Buried P-top Lateral Diffused Metal-Oxide-Semiconductor Devices
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;張怡楓;Chang, Yi-Fong;曹世昌;Tsaur, Shyh-Chang |
| 亞洲大學 |
2010-03 |
Combining 2D and 3D Device Simulations for Optimizing LDMOS Design
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-03 |
Reduction of Kink Effect in SOI LDMOS Structure with Linear Drift Region Thickness
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-03 |
Comparison of High Voltage (200-300 Volts) Lateral Power MOSFETs for Power Integrated Circuits
|
許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;陳兆南 |
| 亞洲大學 |
2010 |
A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques
|
郭宇?;GUO, Yu-Feng;王志功;WANG, Zhi-Gong;許健;Sheu, Gene |
| 亞洲大學 |
2009.08 |
Dependence of Breakdown Voltage on Drift Length and Linear Doping Gradients in SOI RESURF LDMOS Devices
|
楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2009.07 |
VARIATION OF LATERAL THICKNESSTECHNIQUES IN SOI LATERAL HIGH VOLTAGE DEVICE
|
郭宇鋒;Guo, Yufeng;王至剛;Wang1, Zhigong;許健;Sheu, Gene |
显示项目 81-90 / 107 (共11页)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
每页显示[10|25|50]项目
|
