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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"許健"的相关文件
显示项目 86-95 / 107 (共11页) << < 2 3 4 5 6 7 8 9 10 11 > >> 每页显示[10|25|50]项目
| 亞洲大學 |
2010-03 |
Reduction of Kink Effect in SOI LDMOS Structure with Linear Drift Region Thickness
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming |
| 亞洲大學 |
2010-03 |
Comparison of High Voltage (200-300 Volts) Lateral Power MOSFETs for Power Integrated Circuits
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許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;陳兆南 |
| 亞洲大學 |
2010 |
A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques
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郭宇?;GUO, Yu-Feng;王志功;WANG, Zhi-Gong;許健;Sheu, Gene |
| 亞洲大學 |
2009.08 |
Dependence of Breakdown Voltage on Drift Length and Linear Doping Gradients in SOI RESURF LDMOS Devices
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楊紹明;Yang, Shao-Ming;許健;Sheu, Gene |
| 亞洲大學 |
2009.07 |
VARIATION OF LATERAL THICKNESSTECHNIQUES IN SOI LATERAL HIGH VOLTAGE DEVICE
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郭宇鋒;Guo, Yufeng;王至剛;Wang1, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009.05 |
A High Performance 80V Smart LDMOS Power Device Based on thin oxide technology
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許健;Sheu, Gene;楊紹明;許愉珊 |
| 亞洲大學 |
2009.03 |
Simulation Details for the Electrical Field Distribution and Breakdown Voltage of0.15μm Thin Film SOI Power Device
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You, Hsin-Chiang;Liu, Yen-Ling;Tsaur, Shyh-chang;許健;Sheu, Gene |
| 亞洲大學 |
2009-12 |
Combining 2D and 3D Device Simulation for Optimizing LDMOS Design
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許健;Sheu, Gene;許健;Sheu, Gene |
| 亞洲大學 |
2009-11 |
A Three-dimensional Breakdown Model of SOI Lateral Power Transistors with a Circular Layout
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郭宇峰;Guo, Yufeng;Wang, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009-08 |
Dependence of Breakdown Voltage on Drift Length and Linear Doping Gradients in SOI RESURF LDMOS Devices
|
許健;Sheu, Gene;許健;Sheu, Gene |
显示项目 86-95 / 107 (共11页) << < 2 3 4 5 6 7 8 9 10 11 > >> 每页显示[10|25|50]项目
|