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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"謝曜式"的相关文件
显示项目 26-35 / 75 (共8页)
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| 中華大學 |
2006 |
A High-Efficient Line-Based Architecture for 2-D Lifting-Based DWT Using 9/7 Wavelet Filters
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
A High-Efficient Image Scalar Algorithm for LCD Signal Processor
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
VLSI Implementation of A High-Efficient Image Scalar Algorithm for LCD Signal Processor
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-Tap Daubechies Filters
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
台灣科技產業結構性改變與管理之變遷
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
A High-Throughput and Memory-Efficiency 2-D DCT Architecture Based on CORDIC Rotation
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering
|
謝曜式; Shieh, Yaw-Shih |
显示项目 26-35 / 75 (共8页)
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