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"dung lr"的相关文件
显示项目 1-20 / 20 (共1页)
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| 國立交通大學 |
2019-04-02T06:04:41Z |
A maskable memory architecture for rank-order filtering
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Lin, MC; Dung, LR |
| 國立交通大學 |
2014-12-08T15:43:41Z |
A reconfigurable architecture for DSP system-on-chip
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Dung, LR; Lee, YL; Wu, CM |
| 國立交通大學 |
2014-12-08T15:43:06Z |
EFBLA: A two-phase matching algorithm for fast motion estimation
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Cheng, HW; Dung, LR |
| 國立交通大學 |
2014-12-08T15:39:41Z |
A vario-power ME architecture using content-based subsample algorithm
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Cheng, HW; Dung, LR |
| 國立交通大學 |
2014-12-08T15:39:18Z |
A maskable memory architecture for rank-order filtering
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Dung, LR; Lin, MC |
| 國立交通大學 |
2014-12-08T15:39:10Z |
EFBLA: a two-phase matching algorithm for fast motion estimation
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Cheng, HW; Dung, LR |
| 國立交通大學 |
2014-12-08T15:39:09Z |
Resonator-based multi-stage Sigma Delta modulator for wideband applications with improved dynamic range
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Chang, TH; Dung, LR |
| 國立交通大學 |
2014-12-08T15:37:16Z |
An IP synthesizer for limited-resource DWT processor
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Dung, LR |
| 國立交通大學 |
2014-12-08T15:37:11Z |
On multiple-voltage high-level synthesis using algorithmic transformations
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Dung, LR; Yang, HC |
| 國立交通大學 |
2014-12-08T15:35:17Z |
Dynamic range improvement of multistage multibit Sigma Delta modulator for low oversampling ratios
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Chang, TH; Dung, LR |
| 國立交通大學 |
2014-12-08T15:27:55Z |
ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN
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SHEN, WZ; TAO, YH; DUNG, LR |
| 國立交通大學 |
2014-12-08T15:26:30Z |
An automated IP synthesizer for limited-resource DWT processor
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Wei, TH; Huang, SR; Dung, LR |
| 國立交通大學 |
2014-12-08T15:26:27Z |
VLSI implememtation for MAC-level DWT architecture
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Huang, SR; Dung, LR |
| 國立交通大學 |
2014-12-08T15:26:16Z |
A novel vario-power architecture of motion estimation using a content-based subsample algorithm
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Cheng, HW; Dung, LR |
| 國立交通大學 |
2014-12-08T15:26:14Z |
A content-based motion estimation algorithm for power-aware architecture
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Cheng, HW; Dung, LR; Yen, JH; Wang, JJ |
| 國立交通大學 |
2014-12-08T15:25:38Z |
On improving dynamic range of wideband multistage Sigma Delta modulator using nonlinear oscillation
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Chang, TH; Dung, LR; Guo, JY |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Modeling and formal verification of dataflow graph in system-level design using Petri net
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Chiang, TH; Dung, LR; Yaung, MF |
| 國立交通大學 |
2014-12-08T15:25:23Z |
Design of power-aware multiplier with graceful quality-power trade-offs
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Yen, JH; Dung, LR; Shen, CY |
| 國立交通大學 |
2014-12-08T15:25:23Z |
On reducing leakage quantization noise of multistage Sigma Delta modulator using nonlinear oscillation
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Chang, TH; Dung, LR; Guo, JY |
| 國立交通大學 |
2014-12-08T15:18:14Z |
A content-based methodology for power-aware motion estimation architecture
|
Cheng, HW; Dung, LR |
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