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Institution	Date	Title	Author
國立交通大學	2020-10-05T02:01:30Z	A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10(12) Endurance	Hsieh, E. R.; Chang, H. Y.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert; Wong, S. Simon
國立交通大學	2020-10-05T02:01:30Z	Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era	Hsieh, E. R.; Wang, H. W.; Liu, C. H.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert
國立交通大學	2020-10-05T02:01:28Z	Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)	Xiao, Y.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert
國立交通大學	2020-10-05T02:01:28Z	High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning	Hsieh, E. R.; Giordano, M.; Hodson, B.; Levy, A.; Osekowsky, S. K.; Radway, R. M.; Shih, Y. C.; Wan, W.; Wu, T. F.; Zheng, X.; Nelson, M.; Le, B. Q.; Wong, H. -S. P.; Mitra, S.; Wong, S.
國立交通大學	2020-07-01T05:20:35Z	The Demonstration of Gate Dielectric -fuse 4kb OTP Memory Feasible for Embedded Applications in High -k Metal-gate CMOS Generations and Beyond	Hsieh, E. R.; Chang, C. W.; Chuang, C. C.; Chen, H. W.; Chung, Steve S.
國立交通大學	2020-01-02T00:03:27Z	The Understanding of Gate Capacitance Matching on Achieving a High Performance NC MOSFET with Sufficient Mobility	Chiang, C. K.; Husan, P.; Lou, Y. C.; Li, F. L.; Hsieh, E. R.; Liu, C. H.; Chung, Steve S.
國立交通大學	2019-06-03T01:09:17Z	An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI	Kuo, J. L.; Chen, H. W.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert
國立交通大學	2019-04-02T06:04:26Z	A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications	Cheng, H. W.; Hsieh, E. R.; Huang, Z. H.; Chuang, C. H.; Chen, C. H.; Li, F. L.; Lo, Y. M.; Liu, C. H.; Chung, Steve S.
國立交通大學	2018-08-21T05:57:09Z	The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing Guidelines	Chung, Steve S.; Hsieh, E. R.
國立交通大學	2018-08-21T05:57:00Z	The Guideline on Designing Face-tunneling FET for Large-scale-device Applications in IoT	Hsieh, E. R.; Lee, J. W.; Lee, M. H.; Chung, Steve S.
國立交通大學	2018-08-21T05:56:52Z	A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance Applications	Hsieh, E. R.; Fan, Y. C.; Chang, K. Y.; Liu, C. H.; Chien, C. H.; Chung, Steve S.
國立交通大學	2018-08-21T05:56:52Z	Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs	Hsieh, E. R.; Fan, Y. C.; Liu, C. H.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R.
國立交通大學	2017-04-21T06:56:06Z	A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors	Hsieh, E. R.; Chung, Steve S.
國立交通大學	2017-04-21T06:50:15Z	A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects	Hung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S.
國立交通大學	2017-04-21T06:50:15Z	A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices	Hsieh, E. R.; Wang, Y. D.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Hsu, S.
國立交通大學	2017-04-21T06:50:00Z	The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices	Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T.
國立交通大學	2017-04-21T06:49:47Z	The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices	Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R.
國立交通大學	2017-04-21T06:49:45Z	Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications	Hsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S.
國立交通大學	2017-04-21T06:49:14Z	A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology	Hsieh, E. R.; Hung, C. M.; Wang, T. Y.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R.
國立交通大學	2017-04-21T06:49:09Z	An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation	Hsieh, E. R.; Chuang, C. H.; Chung, Steve S.
國立交通大學	2017-04-21T06:49:07Z	Experimental Techniques on the Understanding of the Charge Loss in a SONOS Nitride-storage Nonvolatile Memory	Hsieh, E. R.; Wang, H. T.; Chung, Steve S.; Chang, Wayne; Wang, S. D.; Chen, C. H.
國立交通大學	2017-04-21T06:49:02Z	A Novel One Transistor Resistance-Gate Nonvolatile Memory	Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H.
國立交通大學	2017-04-21T06:48:46Z	A Novel One Transistor Non-volatile Memory Feasible for NOR and NAND Applications in IoT Era	Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H.
國立交通大學	2017-04-21T06:48:18Z	The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown	Hsieh, E. R.; Huang, Z. H.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R.
國立交通大學	2016-03-28T00:04:19Z	The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement	Hsieh, E. R.; Chung, Steve S.
國立交通大學	2015-12-02T03:00:54Z	The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices	Wu, P. C.; Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T.
國立交通大學	2015-07-21T08:31:06Z	Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Trigate MOSFETs and the Power Dissipation of SRAM	Hsieh, E. R.; Lin, S. T.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Jung, L. T.
國立交通大學	2014-12-16T06:15:13Z	Structure and process of basic complementary logic gate made by junctionless transistors	Chung Steve S.; Hsieh E. R.
國立交通大學	2014-12-08T15:48:25Z	The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology	Hsieh, E. R.; Chang, Derrick W.; Chung, S. S.; Lin, Y. H.; Tsai, C. H.; Tsai, C. T.; Ma, G. H.
國立交通大學	2014-12-08T15:48:21Z	New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyond	Hsieh, E. R.; Chung, Steve S.; Lin, Y. H.; Tsai, C. H.; Liu, P. W.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.
國立交通大學	2014-12-08T15:45:53Z	More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable Reliability	Chung, Steve S.; Hsieh, E. R.; Huang, D. C.; Lai, C. S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.
國立交通大學	2014-12-08T15:39:25Z	The Understanding of Strain-Induced Device Degradation in Advanced MOSFETs with Process-Induced Strain Technology of 65nm Node and Beyond	Lin, M. H.; Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.
國立交通大學	2014-12-08T15:36:22Z	The understanding of the drain-current fluctuation in a silicon-carbon source-drain strained n-channel metal-oxide-semiconductor field-effect transistors	Hsieh, E. R.; Chung, Steve S.
國立交通大學	2014-12-08T15:32:43Z	The Understanding of the Bulk Trigate MOSFET's Reliability Through the Manipulation of RTN Traps	Hsieh, E. R.; Wu, P. C.; Chung, Steve S.; Tsai, C. H.; Huang, R. M.; Tsai, C. T.
國立交通大學	2014-12-08T15:30:46Z	The Understanding of Multi-level RTN in Trigate MOSFETs Through the 2D Profiling of Traps and Its Impact on SRAM Performance: A New Failure Mechanism Found	Hsieh, E. R.; Tsai, Y. L.; Chung, Steve S.; Tsai, C. H.; Huang, R. M.; Tsai, C. T.
國立交通大學	2014-12-08T15:28:53Z	The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors	Hsieh, E. R.; Chung, Steve S.
國立交通大學	2014-12-08T15:28:02Z	Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC Applications	Yang, C. L.; Tsai, C. H.; Li, C. I.; Tzeng, C. Y.; Lin, G. P.; Chen, W. J.; Chin, Y. L.; Liao, C. I.; Chan, M.; Wu, J. Y.; Hsieh, E. R.; Guo, B. N.; Lu, S.; Colombeau, B.; Chung, S. S.; Chen, I. C.
國立交通大學	2014-12-08T15:22:00Z	A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement	Lin, M. H.; Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.
國立交通大學	2014-12-08T15:21:56Z	Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)	Chung, Steve S.; Hsieh, E. R.; Liu, P. W.; Chiang, W. T.; Tsai, S. H.; Tsai, T. L.; Huang, R. M.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.
國立交通大學	2014-12-08T15:21:21Z	A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime	Hsieh, E. R.; Chung, Steve S.; Liu, P. W.; Chiang, W. T.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.
國立交通大學	2014-12-08T15:20:29Z	New Observations on the Physical Mechanism of Vth-Variation in Nanoscale CMOS Devices After Long Term Stress	Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Huang, R. M.; Tsai, C. T.; Liang, C. W.
國立交通大學	2014-12-08T15:07:17Z	The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors	Hsieh, E. R.; Chung, Steve S.

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