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"hsieh e r"的相关文件
显示项目 1-25 / 42 (共2页)
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| 國立交通大學 |
2020-10-05T02:01:30Z |
A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10(12) Endurance
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Hsieh, E. R.; Chang, H. Y.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert; Wong, S. Simon |
| 國立交通大學 |
2020-10-05T02:01:30Z |
Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
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Hsieh, E. R.; Wang, H. W.; Liu, C. H.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert |
| 國立交通大學 |
2020-10-05T02:01:28Z |
Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)
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Xiao, Y.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert |
| 國立交通大學 |
2020-10-05T02:01:28Z |
High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
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Hsieh, E. R.; Giordano, M.; Hodson, B.; Levy, A.; Osekowsky, S. K.; Radway, R. M.; Shih, Y. C.; Wan, W.; Wu, T. F.; Zheng, X.; Nelson, M.; Le, B. Q.; Wong, H. -S. P.; Mitra, S.; Wong, S. |
| 國立交通大學 |
2020-07-01T05:20:35Z |
The Demonstration of Gate Dielectric -fuse 4kb OTP Memory Feasible for Embedded Applications in High -k Metal-gate CMOS Generations and Beyond
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Hsieh, E. R.; Chang, C. W.; Chuang, C. C.; Chen, H. W.; Chung, Steve S. |
| 國立交通大學 |
2020-01-02T00:03:27Z |
The Understanding of Gate Capacitance Matching on Achieving a High Performance NC MOSFET with Sufficient Mobility
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Chiang, C. K.; Husan, P.; Lou, Y. C.; Li, F. L.; Hsieh, E. R.; Liu, C. H.; Chung, Steve S. |
| 國立交通大學 |
2019-06-03T01:09:17Z |
An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI
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Kuo, J. L.; Chen, H. W.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert |
| 國立交通大學 |
2019-04-02T06:04:26Z |
A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications
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Cheng, H. W.; Hsieh, E. R.; Huang, Z. H.; Chuang, C. H.; Chen, C. H.; Li, F. L.; Lo, Y. M.; Liu, C. H.; Chung, Steve S. |
| 國立交通大學 |
2018-08-21T05:57:09Z |
The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing Guidelines
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Chung, Steve S.; Hsieh, E. R. |
| 國立交通大學 |
2018-08-21T05:57:00Z |
The Guideline on Designing Face-tunneling FET for Large-scale-device Applications in IoT
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Hsieh, E. R.; Lee, J. W.; Lee, M. H.; Chung, Steve S. |
| 國立交通大學 |
2018-08-21T05:56:52Z |
A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance Applications
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Hsieh, E. R.; Fan, Y. C.; Chang, K. Y.; Liu, C. H.; Chien, C. H.; Chung, Steve S. |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs
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Hsieh, E. R.; Fan, Y. C.; Liu, C. H.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:56:06Z |
A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors
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Hsieh, E. R.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects
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Hung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices
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Hsieh, E. R.; Wang, Y. D.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Hsu, S. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
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Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T. |
| 國立交通大學 |
2017-04-21T06:49:47Z |
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
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Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:49:45Z |
Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications
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Hsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:14Z |
A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
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Hsieh, E. R.; Hung, C. M.; Wang, T. Y.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:49:09Z |
An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation
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Hsieh, E. R.; Chuang, C. H.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:07Z |
Experimental Techniques on the Understanding of the Charge Loss in a SONOS Nitride-storage Nonvolatile Memory
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Hsieh, E. R.; Wang, H. T.; Chung, Steve S.; Chang, Wayne; Wang, S. D.; Chen, C. H. |
| 國立交通大學 |
2017-04-21T06:49:02Z |
A Novel One Transistor Resistance-Gate Nonvolatile Memory
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Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H. |
| 國立交通大學 |
2017-04-21T06:48:46Z |
A Novel One Transistor Non-volatile Memory Feasible for NOR and NAND Applications in IoT Era
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Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H. |
| 國立交通大學 |
2017-04-21T06:48:18Z |
The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
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Hsieh, E. R.; Huang, Z. H.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2016-03-28T00:04:19Z |
The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement
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Hsieh, E. R.; Chung, Steve S. |
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