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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"huang shih hsu"的相關文件
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| 中原大學 |
2002-08 |
Performance and Power Driven Non-Zero Skew Clock Tree Design Methodology
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Huang, Shih-Hsu;Lin, Yu-Hui |
| 中原大學 |
2001-05 |
An Efficient Membership Function Representation for High-Resolution Fuzzy Systems
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Huang, Shih-Hsu;Lai, Jian-Yuan |
| 中原大學 |
2000-12 |
An Interconnect-Driven Low Power Design Methodology
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Huang, Shih-Hsu;Hsiao, Hsu-Ming |
| 中原大學 |
2000-08 |
A New Scheduling Algorithm for Automatic Synthesis of the Control Blocks of Multi-way Branch Architectures
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Huang, Shih-Hsu |
| 中原大學 |
1999-12 |
A Practical Clock Tree Synthesis Flow
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Chi, Chen Mely;Huang, Shih-Hsu |
| 中原大學 |
1999-12 |
A Practical Clock Tree Synthesis Flow
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Chi, Mely-Chen;Huang, Shih-Hsu |
| 國立臺灣大學 |
1995 |
A new approach to schedule operations across nested-ifs and nested-loops
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Huang, Shih-Hsu; Hwang, Cheng-Tsung; Hsu, Yu-Chin; Oyang, Yen-Jen |
| 國立臺灣大學 |
1995 |
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits
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Huang, Shih-Hsu; Hsu, Yu-Chin; Oyang, Yen-Jen |
| 臺大學術典藏 |
1995 |
A new approach to schedule operations across nested-ifs and nested-loops
|
Huang, Shih-Hsu; Hwang, Cheng-Tsung; Hsu, Yu-Chin; Oyang, Yen-Jen; Huang, Shih-Hsu; Hwang, Cheng-Tsung; Hsu, Yu-Chin; Oyang, Yen-Jen |
| 臺大學術典藏 |
1995 |
Synthesis of false loop free circuits.
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Huang, Shih-Hsu; Liu, Ta-Yung; Hsu, Yu-Chin; Oyang, Yen-Jen; YEN-JEN OYANG |
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