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Showing items 1-6 of 6 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:49:36Z |
Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried Oxide
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Kim, Keunwoo; Kuang, Jente B.; Gebara, Fadi; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J. |
| 國立交通大學 |
2014-12-08T15:42:37Z |
An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
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Mukhopadhyay, Saibal; Kim, Keunwoo; Jenkins, Keith A.; Chuang, Ching-Te; Roy, Kaushik |
| 國立交通大學 |
2014-12-08T15:10:57Z |
Optimal design of triple-gate devices for high-performance and low-power applications
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Chiang, Meng-Hsueh; Lin, Jeng-Nan; Kim, Keunwoo; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:10:02Z |
Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap
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Wei, Lan; Deng, Jie; Chang, Li-Wen; Kim, Keunwoo; Chuang, Ching-Te; Wong, H. -S. Philip |
| 國立交通大學 |
2014-12-08T15:08:11Z |
TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability
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Kim, Keunwoo; Kuang, Jente B.; Gebara, Fadi H.; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J. |
| 國立成功大學 |
2012-05 |
Assessment of structure variation in silicon nanowire FETs and impact on SRAM
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Liao, Yi-Bo; Chiang, Meng-Hsueh; Kim, Keunwoo; Hsu, Wei-Chou |
Showing items 1-6 of 6 (1 Page(s) Totally)
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