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Taiwan Academic Institutional Repository >
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"kuo j b"
Showing items 36-45 of 128 (13 Page(s) Totally)
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| 國立臺灣大學 |
2002 |
0.8V CMOS Adiabatic Differential Switch Logic Circuit Using Bootstrap Technique for Low-Voltage Low-Power VLSI
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Zhang, Y.; Chen, H.H.; Kuo, J.B. |
| 國立臺灣大學 |
2002 |
Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneously
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Lin, Shih-Chia; Kuo, J.B. |
| 國立臺灣大學 |
2002 |
Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion
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Lin, Shih-Chia; Kuo, J.B. |
| 國立臺灣大學 |
2001 |
A Novel Low-Voltage Content-Addressable-Memory (CAM) Cell with a Fast Tag-Compare Capability using Partially-Depleted (PD) SOI CMOS Dynamic-Threshold (DTMOS) Techniques
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Liu, S.C.; Wu, F.A.; Kuo, J.B. |
| 國立臺灣大學 |
2001 |
A 1-V 128-kb four-way set-associative CMOS cache memory usingwordline-oriented tag-compare (WLOTC) structure with thecontent-addressable-memory (CAM) 10-transistor tag cell
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Lin, Perng-Fei; Kuo, J.B. |
| 國立臺灣大學 |
2000-08 |
A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique
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Wang, Bo-Ting; Kuo, J.B. |
| 國立臺灣大學 |
2000-06 |
Short-channel effects of SOI partially-depleted (PD) dynamic-threshold MOS (DTMOS) devices
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Lin, S.C.; Yuan, K.H.; Kuo, J.B. |
| 國立臺灣大學 |
2000-06 |
SPICE compact modeling of PD-SOI CMOS devices
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Kuo, J.B. |
| 臺大學術典藏 |
2000-06 |
SPICE compact modeling of PD-SOI CMOS devices
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Kuo, J.B.; Kuo, J.B.; KuoJB |
| 國立臺灣大學 |
2000-05 |
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
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Wang, B.T.; Kuo, J.B. |
Showing items 36-45 of 128 (13 Page(s) Totally)
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