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"kuo po yi"的相關文件
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| 國立交通大學 |
2020-02-01 |
Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
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Chao, Tien-Sheng; Chen, Hsin-Yu; Huang, Yu-En; Chung, Chun-Chih; Shen, Chiuan-Huei; Kuo, Po-Yi; Lee, Shen-Yang; Chen, Han-Wei |
| 國立交通大學 |
2020-01-02T00:03:25Z |
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
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Lee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng |
| 國立交通大學 |
2019-12-13T01:12:24Z |
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
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Lee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng |
| 國立交通大學 |
2019-08-02T02:18:32Z |
Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage
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Kuo, Po-Yi; Chang, Chien-Min; Liu, I-Han; Liu, Po-Tsun |
| 國立交通大學 |
2019-06-03T01:09:16Z |
Low Thermal Budget Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Near Ideal Subthreshold Swing
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Kuo, Po-Yi; Chang, Chien-Min; Liu, Po-Tsun |
| 國立交通大學 |
2019-04-02T06:04:16Z |
Back-Channel Etched Double Layer In-W-O/In-W-Zn-O Thin-Film Transistors
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Li, Zhen-Hao; Kuo, Po-Yi; Chen, Wen-Tzu; Liu, Po-Tsun |
| 國立交通大學 |
2019-04-02T06:04:16Z |
High Performance Amorphous In-W-Zn-O Thin Film Transistor with Ultra-Thin Active Channel for Low Voltage Operation
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Liu, Po-Tsun; Kuo, Po-Yi; Hsu, Shan-Ming |
| 國立交通大學 |
2019-04-02T06:00:27Z |
The influence on electrical characteristics of amorphous indium tungsten oxide thin film transistors with multi-stacked active layer structure
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Ruan, Dun-Bao; Liu, Po-Tsun; Gan, Kai-Jhih; Chiu, Yu-Chuan; Yu, Min-Chin; Chien, Ta-Chun; Chen, Yi-Heng; Kuo, Po-Yi; Sze, Simon M. |
| 國立交通大學 |
2019-04-02T05:59:59Z |
Performance improvements of tungsten and zinc doped indium oxide thin film transistor by fluorine based double plasma treatment with a high-K gate dielectric
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Yu, Min-Chin; Gan, Kai-Jhih; Chien, Ta-Chun; Chen, Yi-Heng; Kuo, Po-Yi; Sze, Simon M. |
| 國立交通大學 |
2019-04-02T05:59:28Z |
Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Kuo, Po-Yi; Yu, Min-Chin; Kan, Kai-Zhi; Chien, Ta-Chun; Chen, Yi-Heng; Sze, Simon M. |
| 國立交通大學 |
2019-04-02T05:58:50Z |
Investigation of low operation voltage InZnSnO thin-film transistors with different high-k gate dielectric by physical vapor deposition
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Kan, Kai-Zhi; Yu, Min-Chin; Chien, Ta-Chun; Chen, Yi-Heng; Kuo, Po-Yi; Sze, Simon M. |
| 國立交通大學 |
2018-08-21T05:56:29Z |
High Mobility Tungsten-Doped Thin-Film Transistor on Polyimide Substrate with Low Temperature Process
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Yu, Min-Chin; Gan, Kai-jhih; Chien, Ta-Chun; Kuo, Po-Yi; Sze, Simon M. |
| 國立交通大學 |
2018-08-21T05:54:11Z |
Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs
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Hsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:29Z |
Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs
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Hsieh, Dong-Ru; Chan, Yi-De; Kuo, Po-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:29Z |
Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity
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Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Lee, Sen-Yang; Chao, Tien-Sheng |
| 國立交通大學 |
2018-08-21T05:53:27Z |
Effects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film Transistors
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Liu, Po-Tsun; Chang, Chih-Hsiang; Kuo, Po-Yi; Chen, Po-Wen |
| 國立交通大學 |
2018-08-21T05:53:19Z |
Mobility enhancement for high stability tungsten-doped indium-zinc oxide thin film transistors with a channel passivation layer
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Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Kuo, Po-Yi; Yu, Min-Chin; Gan, Kai-Jhih; Chien, Ta-Chun; Sze, Simon M. |
| 國立交通大學 |
2017-04-21T06:56:35Z |
High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique
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Hsieh, Dong-Ru; Kuo, Po-Yi; Lin, Jer-Yi; Chen, Yi-Hsuan; Chang, Tien-Shun; Chao, Tien-Sheng |
| 國立交通大學 |
2017-04-21T06:56:21Z |
Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
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Lin, Jer-Yi; Kuo, Po-Yi; Lin, Ko-Li; Chin, Chun-Chieh; Chao, Tien-Sheng |
| 國立交通大學 |
2017-04-21T06:55:58Z |
High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET
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Hsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2017-04-21T06:48:46Z |
Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC Applications
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Hsieh, Don-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2017-04-21T06:48:18Z |
Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swing
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Kuo, Po-Yi; Lin, Jer-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2015-07-21T11:20:46Z |
High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n(+)-Doped Poly-Si NWs Channels Junctionless FETs
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Kuo, Po-Yi; Lu, Yi-Hsien; Chao, Tien-Sheng |
| 國立交通大學 |
2014-12-16T06:14:01Z |
Manufacturing method of a semiconductor component with a nanowire channel
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Kuo Po-Yi; Chao Tien-Sheng; Lu Yi-Hsien |
| 國立交通大學 |
2014-12-08T15:48:37Z |
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
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Chiang, Tsung-Yu; Wu, Yi-Hong; Ma, William Cheng-Yu; Kuo, Po-Yi; Wang, Kuan-Ti; Liao, Chia-Chun; Yeh, Chi-Ruei; Yang, Wen-Luh; Chao, Tien-Sheng |
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