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Taiwan Academic Institutional Repository >
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"lai feipei"
Showing items 226-235 of 253 (26 Page(s) Totally) << < 17 18 19 20 21 22 23 24 25 26 > >> View [10|25|50] records per page
| 國立彰化師範大學 |
1996-10 |
Image Shading Taking into Account Relativistic Effects
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Chang, Meng-chou; Lai, Feipei; Chen, Wei-chao |
| 國立彰化師範大學 |
1996-03 |
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme
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Chang, Meng-chou; Lai, Feipei |
| 國立臺灣大學 |
1995-08 |
A simple tree pattern matching algorithm for code generator
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Chen, Tzer-Shyong; Lai, Feipei; Shang, Rung-Ji |
| 國立臺灣大學 |
1994-12 |
A performance evaluation procedure for a class of growable ATM switches
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Tsai, Zsehong; Yu, Kangyei; Lai, Feipei |
| 臺大學術典藏 |
1994-12 |
A performance evaluation procedure for a class of growable ATM switches
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Tsai, Zsehong; Yu, Kangyei; Lai, Feipei; Tsai, Zsehong; Yu, Kangyei; Lai, Feipei; TsaiZsehong |
| 國立臺灣大學 |
1994-05 |
The complementary relationship of interprocedural register allocation and inlining
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Lai, Feipei; Chao, Yung-Kuang |
| 國立彰化師範大學 |
1994-03 |
A Superscalar Micro-architecture Supporting Aggressive Instruction Scheduling
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Chang, Meng-chou; Lai, Feipei |
| 國立臺灣大學 |
1994-01 |
A pipeline bubbles reduction technique for the Monsoon dataflow architecture
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Lai, Feipei; Tsai, Fong-Chou |
| 國立臺灣大學 |
1993-10 |
Arden - Architecture Development Environment
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Lai, Feipei; Hwang, Shu-Lin; Chen, Tzer-Shyong; Hsieh, Chia-Rung |
| 國立彰化師範大學 |
1992-12 |
Exploiting Instruction-Level Parallelism with the Conjugate Register File Scheme
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Chang, Meng-chou; Lai, Feipei; Shang, Rung-ji |
Showing items 226-235 of 253 (26 Page(s) Totally) << < 17 18 19 20 21 22 23 24 25 26 > >> View [10|25|50] records per page
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