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| 臺大學術典藏 |
2022-02-21T23:31:00Z |
Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
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Wu, Mu Ting; Kuo, Cheng Sian; Li, James Chien Mo; Nigh, Chris; Bhargava, Gaurav |
| 臺大學術典藏 |
2022-02-21T23:31:00Z |
Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
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Kuo, Yen Ting; Lin, Wei Chen; Chen, Chun; Hsieh, Chao Ho; Li, James Chien Mo; Jia-Wei Fang, Eric; Hsueh, Sung S.Y. |
| 臺大學術典藏 |
2021-03-03T05:33:58Z |
QATG: Automatic Test Generation for Quantum Circuits
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Wu, Chen Hung; Hsieh, Cheng Yun; JIUN-YUN LI; Li, James Chien Mo |
| 臺大學術典藏 |
2020-06-29T01:20:12Z |
Physical-aware diagnosis of multiple interconnect defects.
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Chen, Po-Hao;Lee, Chi-Lin;Chen, Jing-Yu;Chen, Po-Wei;Li, James Chien-Mo; Chen, Po-Hao; Lee, Chi-Lin; Chen, Jing-Yu; Chen, Po-Wei; Li, James Chien-Mo; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:11Z |
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.
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Chen, Yo-Wei; Pan, Cheng-Sheng; Li, James Chien-Mo; CHIEN-MO LI; Ho, Yu-Hao; Chiang, Kuan-Ying; Chiang, Kuan-Ying;Ho, Yu-Hao;Chen, Yo-Wei;Pan, Cheng-Sheng;Li, James Chien-Mo |
| 臺大學術典藏 |
2020-06-29T01:20:11Z |
Test Pattern Compression for Probabilistic Circuits.
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Chang, Chih-Ming;Yang, Kai-Jie;Li, James Chien-Mo;Chen, Hung; Chang, Chih-Ming; Yang, Kai-Jie; Li, James Chien-Mo; Chen, Hung; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:11Z |
GPU-based timing-aware test generation for small delay defects.
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Liao, Kuan-Yu;Chen, Po-Juei;Lin, Ang-Feng;Li, James Chien-Mo;Hsiao, Michael S.;Wang, Laung-Terng; Liao, Kuan-Yu; Chen, Po-Juei; Lin, Ang-Feng; Li, James Chien-Mo; Hsiao, Michael S.; Wang, Laung-Terng; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:10Z |
Test Generation of Path Delay Faults Induced by Defects in Power TSV.
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Shih, Chi-Jih;Hsieh, Shih-An;Lu, Yi-Chang;Li, James Chien-Mo;Wu, Tzong-Lin;Chakrabarty, Krishnendu; Shih, Chi-Jih; Hsieh, Shih-An; Lu, Yi-Chang; Li, James Chien-Mo; Wu, Tzong-Lin; Chakrabarty, Krishnendu; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:09Z |
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits.
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Shen, Shiue-Tsung;Liu, Wei-Hsiao;Ma, En-Hua;Li, James Chien-Mo;Cheng, I-Chun; Shen, Shiue-Tsung; Liu, Wei-Hsiao; Ma, En-Hua; Li, James Chien-Mo; Cheng, I-Chun; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-16T06:31:35Z |
BIST design optimization for large-scale embedded memory cores.
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Chien, Tzuo-Fan;Chao, Wen-Chi;Li, James Chien-Mo;Chang, Yao-Wen;Liao, Kuan-Yu;Chang, Ming-Tung;Tsai, Min-Hsiu;Tseng, Chih-Mou; Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; Tseng, Chih-Mou; YAO-WEN CHANG |
Showing items 1-10 of 20 (2 Page(s) Totally)
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