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"liang yung chih"
Showing items 1-5 of 5 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:50:01Z |
Design of Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage against Mis-trigger or Transient-Induced Latch-On Events
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Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:53Z |
Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
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Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:51Z |
Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
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Yeh, Chih-Ting; Ker, Ming-Dou; Liang, Yung-Chih |
| 淡江大學 |
2011-01 |
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
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Yang, Wei-Bin; Liao, Chao-Cheng; Liang, Yung-Chih |
| 淡江大學 |
2008-11 |
A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
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Liang, Yung-chih; Huang, Ching-ji; Yang, Wei-bin |
Showing items 1-5 of 5 (1 Page(s) Totally)
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