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Showing items 1-13 of 13 (1 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T04:15:44Z |
Energy Analysis of Bipartition Architecture for Pipelined Circuits
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Ruan, Shanq-Jang;Naroska, Edwin;Chang, Yen-Ren;Ho, Chia-Lin;Lai, Feipei; Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Ren; Ho, Chia-Lin; Lai, Feipei; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T04:15:43Z |
Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits
|
Ruan, Shanq-Jang; Ho, Chia-Lin; Naroska, Edwin; Lai, Feipei; FEI-PEI LAI |
| 臺大學術典藏 |
2018-09-10T03:51:00Z |
Multimedia ASIP SoC Codesign Based on Multicriteria Optimization
|
Jeng, I-Horng; Lai, Feipei; Naroska, Edwin; Schwiegelshohn, Uwe; FEI-PEI LAI |
| 臺大學術典藏 |
2005-06 |
Optimal Permutation and Spacing for Unbiased Random, Counter, and Instruction Address Buses
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Naroska, Edwin; Ruan, Shanq-Jang; Uwe Schwiegelshohn; Lai, Feipei; FEI-PEI LAI |
| 國立臺灣大學 |
2005 |
Bipartitioning and encoding in low-power pipelined circuits
|
Ruan, Shanq-Jang; Tsai, Kun-Lin; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2005 |
Low Power Dynamic Bus Encoding for Deep Sub-micron Design
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Tsai, Kun-Lin; Ruan, Shanq-Jang; Chen, Li-Wei; Lai Feipei; Naroska, Edwin |
| 國立臺灣大學 |
2005 |
Optimal Permutation and Spacing for Unbiased Random, Counter, and Instruction Address Buses
|
Naroska, Edwin; Ruan, Shanq-Jang; Uwe Schwiegelshohn; Lai, Feipei |
| 國立臺灣大學 |
2004 |
Circuit Partition and Reordering Technique for Low Power IP
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Tsai, Kun-Lin; Ruan, Shanq-Jang; Huang, Chun-Ming; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2002-10 |
Energy analysis of bipartition architecture for pipelined circuits
|
Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Ren; Ho, Chia-Lin; Lai, Feipei |
| 國立臺灣大學 |
2002-09 |
Power analysis of bipartition and dual-encoding architecture for pipelined circuits
|
Ruan, Shanq-Jang; Ho, Chia-Lin; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2002 |
ENPCO: An Entropy-Based Partition-Codec Algorithm to Reduce Power for bipartition-codec architecture in Pipelined Circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Jen; Lai, Feipei; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001-06 |
Multimedia ASIP SoC codesign based on multicriteria optimization
|
Jeng, I-Horng; Lai, Feipei; Naroska, Edwin; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001 |
Efficient parallel timing simulation of synchronous models on networks of workstations
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Naroska, Edwin; Lai, Feipei; Shang, Rung-Ji; Schwiegelshohn, Uwe |
Showing items 1-13 of 13 (1 Page(s) Totally)
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