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机构 日期 题名 作者
臺大學術典藏 2019-10-24T07:45:22Z Sequential Engineering Change Order under Retiming and Resynthesis 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Victor Kravets;Nian-Ze Lee; Nian-Ze Lee; Victor Kravets; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:22Z Sequential Engineering Change Order under Retiming and Resynthesis 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Victor Kravets;Nian-Ze Lee; Nian-Ze Lee; Victor Kravets; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:21Z Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:21Z Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:21Z Solving Stochastic Boolean Satisfiability under Random-Exist Quantification 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Yen-Shi Wang;Nian-Ze Lee; Nian-Ze Lee; Yen-Shi Wang; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:21Z Solving Stochastic Boolean Satisfiability under Random-Exist Quantification 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Yen-Shi Wang;Nian-Ze Lee; Nian-Ze Lee; Yen-Shi Wang; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:20Z Towards Formal Evaluation and Verification of Probabilistic Design 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Nian-Ze Lee; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:45:20Z Towards Formal Evaluation and Verification of Probabilistic Design 江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Nian-Ze Lee; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏 2019-10-24T07:43:08Z Solving Stochastic Boolean Satisfiability under Random-Exist Quantification JIE-HONG JIANG;Jie-Hong R. Jiang;Yen-Shi Wang;Nian-Ze Lee; Nian-Ze Lee; Yen-Shi Wang; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:08Z Solving Stochastic Boolean Satisfiability under Random-Exist Quantification JIE-HONG JIANG;Jie-Hong R. Jiang;Yen-Shi Wang;Nian-Ze Lee; Nian-Ze Lee; Yen-Shi Wang; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:08Z Sequential Engineering Change Order under Retiming and Resynthesis JIE-HONG JIANG;Jie-Hong R. Jiang;Victor Kravets;Nian-Ze Lee; Nian-Ze Lee; Victor Kravets; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:08Z Sequential Engineering Change Order under Retiming and Resynthesis JIE-HONG JIANG;Jie-Hong R. Jiang;Victor Kravets;Nian-Ze Lee; Nian-Ze Lee; Victor Kravets; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:07Z Towards Formal Evaluation and Verification of Probabilistic Design JIE-HONG JIANG;Jie-Hong R. Jiang;Nian-Ze Lee; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:07Z Towards Formal Evaluation and Verification of Probabilistic Design JIE-HONG JIANG;Jie-Hong R. Jiang;Nian-Ze Lee; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:07Z Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2019-10-24T07:43:07Z Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2018-09-10T15:00:43Z Towards Formal Evaluation and Verification of Probabilistic Design Nian-Ze Lee;Jie-Hong R. Jiang; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏 2018-09-10T15:00:43Z Towards Formal Evaluation and Verification of Probabilistic Design Nian-Ze Lee;Jie-Hong R. Jiang; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG

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