English  |  正體中文  |  简体中文  |  2816738  
???header.visitor??? :  27578692    ???header.onlineuser??? :  583
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

"r t hwang"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1??? ???jsp.browse.items-by-author.order2???

Showing items 1-9 of 9  (1 Page(s) Totally)
1 
View [10|25|50] records per page

Institution Date Title Author
國立中山大學 2000-01 Single-ended SRAM with high test coverage and short test time C.C. Wang;C.F. Wu;R.T. Hwang; C.H. Kao
國立中山大學 2000 Single-ended SRAM with high test coverage and short test time C.C. Wang;C.F. Wu;R.T. Hwang;C.H. Kao
國立中山大學 1999-07 A low-power high-speed dynamic PLA circuit configuration for single-clock CMOS C.C. Wang;C.F. Wu; R.T. Hwang;C.H. Kao
國立中山大學 1999-01 Dynamic NOR-NOR PLA Design with IDDQ Testability C.F. Wu;C.C. Wang;R.T. Hwang;C.H. Kao
國立中山大學 1999 Dynamic NOR-NOR PLA Design with IDDQ Testability C.F. Wu;C.C. Wang;R.T. Hwang;C.H. Kao
國立中山大學 1999 A low-power high-speed dynamic PLA circuit configuration for single-clock CMOS C.C. Wang;C.F. Wu;R.T. Hwang;C.H. Kao
國立中山大學 1998-06 Design of single-ended SRAM with high test coverage and short test time C.F. Wu;C.C. Wang;R.T. Hwang;C.H. Kao
國立中山大學 1997-12 A low-power and high-speed dynmaic PLA circuit configurationfor single-clock CMOS C.C. Wang;C.F. Wu;R.T. Hwang;C.H. Kao
國立中山大學 1997-09 IDDQ testable configuration for PLAs by transformation into inverters C.F. Wu;C.C. Wang;R.T. Hwang;C.H. Kao

Showing items 1-9 of 9  (1 Page(s) Totally)
1 
View [10|25|50] records per page