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"tziantzioulis g"
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| 國立成功大學 |
2023 |
CIFER: A Cache-Coherent 12-nm 16-mm2SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2Synthesizable eFPGA
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Li, A.;Chang, T.-J.;Gao, F.;Ta, Ta T.;Tziantzioulis, G.;Ou, Y.;Wang, M.;Tu, J.;Xu, K.;Jackson, P.;Ning, A.;Chirkov, G.;Orenes-Vera, M.;Agwa, S.;Yan, X.;Tang, E.;Balkind, J.;Batten, C.;Wentzlaff, D. |
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