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"wey i c"的相關文件
顯示項目 1-11 / 11 (共1頁)
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| 臺大學術典藏 |
2018-09-10T07:04:42Z |
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation
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Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:42Z |
Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits
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Wey, I.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:54Z |
Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules
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Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design
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Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement
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Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A clock-fault tolerant architecture and circuit for reliable nanoelectronics system
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Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:15Z |
A scalable DCO design for portable ADPLL designs
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Wu, C.-T.; Wang, W.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T05:24:14Z |
A high-speed scalable shift-register based on-chip serial communication design for SoC applications
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Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T. |
| 臺大學術典藏 |
2018-09-10T04:56:05Z |
A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design
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Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2006 |
A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment
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Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
顯示項目 1-11 / 11 (共1頁)
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