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Taiwan Academic Institutional Repository >
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"wu an yeu"
Showing items 51-60 of 109 (11 Page(s) Totally)
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| 國立臺灣大學 |
2006 |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed–Solomon Decoder Design Based on Unified Finite-Field Processing Element
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Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
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Lin, Chih-Hsiu; Wu, An-Yeu; Li, Fan-Min |
| 國立臺灣大學 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-12 |
A new stopping criterion for efficient early termination in turbo decoder designs
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Li, Fan-Min; Wu, An-Yeu |
| 臺大學術典藏 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu; Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-07 |
A high speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chen, You-Gang; Wu, Chia-Tsun; Wang, Wei; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A scalable DCO design for portable ADPLL designs
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chang, Lung-Hao; Chen, You-Gang; Chang, Shih-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
Digital signal processing engine design for polar transmitter in wireless communication systems
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Ko, Hung-Yang; Wang, Yi-Chiuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-03 |
Low cost decision feedback equalizer (DFE) design for Giga-bit systems
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Lin, Chih-Hsiu; Wu, An-Yeu |
Showing items 51-60 of 109 (11 Page(s) Totally)
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