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"wu an yeu"的相关文件
显示项目 51-75 / 109 (共5页)
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| 國立臺灣大學 |
2006 |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed–Solomon Decoder Design Based on Unified Finite-Field Processing Element
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Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
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Lin, Chih-Hsiu; Wu, An-Yeu; Li, Fan-Min |
| 國立臺灣大學 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-12 |
A new stopping criterion for efficient early termination in turbo decoder designs
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Li, Fan-Min; Wu, An-Yeu |
| 臺大學術典藏 |
2005-12 |
Polar transmitter for wireless communication system
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Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu; Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai; Jheng, Kai-Yuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-07 |
A high speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chen, You-Gang; Wu, Chia-Tsun; Wang, Wei; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A scalable DCO design for portable ADPLL designs
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Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications
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Wey, I-Chyn; Chang, Lung-Hao; Chen, You-Gang; Chang, Shih-Hung; Wu, An-Yeu |
| 國立臺灣大學 |
2005-05 |
Digital signal processing engine design for polar transmitter in wireless communication systems
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Ko, Hung-Yang; Wang, Yi-Chiuan; Wu, An-Yeu |
| 國立臺灣大學 |
2005-03 |
Low cost decision feedback equalizer (DFE) design for Giga-bit systems
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Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2005 |
Soft-Threshold-Based MultiLayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture
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Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
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Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
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Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
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Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
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Hsu, H.-Y. and Yeo, J.-C. and Wu, A.-Y.; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
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Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
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Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
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Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
Least squares approximation-based ROM-free direct digital frequency synthesizer
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Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu; Wen, Ching-Hua; Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
1000BASE-T Gigabit Ethernet baseband DSP IC design
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Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu; Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
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Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
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Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
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Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
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Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 國立臺灣大學 |
2004 |
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
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Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
显示项目 51-75 / 109 (共5页)
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