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"wu cy"
Showing items 371-395 of 607 (25 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:04:41Z |
A NEW OXIDATION-RESISTANT COSI2 PROCESS FOR SELF-ALIGNED SILICIDATION (SALICIDE) TECHNOLOGY
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LOU, YS; WU, CY; CHENG, HC |
| 國立交通大學 |
2014-12-08T15:04:34Z |
A NEW IV MODEL FOR SHORT GATE-LENGTH MESFETS
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CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:25Z |
DESIGN AND APPLICATION OF PIPELINED DYNAMIC CMOS TERNARY LOGIC AND SIMPLE TERNARY DIFFERENTIAL LOGIC
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WU, CY; HUANG, HY |
| 國立交通大學 |
2014-12-08T15:04:23Z |
A NEW GRID-GENERATION METHOD FOR 2-D SIMULATION OF DEVICES WITH NONPLANAR SEMICONDUCTOR SURFACE
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CHIN, SP; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:22Z |
A NEW 2D ANALYTIC THRESHOLD-VOLTAGE MODEL FOR FULLY DEPLETED SHORT-CHANNEL SOI MOSFETS
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GUO, JY; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:22Z |
THE DESIGN OF FULLY DIFFERENTIAL CMOS OPERATIONAL-AMPLIFIERS WITHOUT EXTRA COMMON-MODE FEEDBACK-CIRCUITS
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LU, PH; WU, CY; TSAI, MK |
| 國立交通大學 |
2014-12-08T15:04:20Z |
A NOVEL PHL-EMITTER BIPOLAR-TRANSISTOR - FABRICATION AND CHARACTERIZATION
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CHANG, KZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:12Z |
NOVEL CHARACTERISTICS OF THE POLYSILICON HIGH-LOW-EMITTER (PHL-EMITTER) BIPOLAR-TRANSISTOR HIGH-CURRENT GAIN AND ZERO ACTIVATION-ENERGY
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CHANG, KZ; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:11Z |
CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:09Z |
TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:09Z |
A CHARACTERIZATION TECHNIQUE FOR THE DEGRADATION CHARACTERISTICS OF TI/SI SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS AFTER THERMAL SILICIDATION
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:08Z |
COMPARATIVE-STUDIES OF GD-ORDERING IN VARIOUS CUPRATE SYSTEMS
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HO, JC; WU, CY; LAI, CC; SHIEH, JH; KU, HC |
| 國立交通大學 |
2014-12-08T15:04:08Z |
MAGNETIC-BEHAVIOR IN PR-CONTAINING TL-BASED AND PB-BASED CUPRATES
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KU, HC; LAI, CC; SHIEH, JH; LIOU, JW; WU, CY; HO, JC |
| 國立交通大學 |
2014-12-08T15:04:02Z |
A SELF-CONSISTENT CHARACTERIZATION METHODOLOGY FOR SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:57Z |
NEW DESIGN METHODOLOGY AND NEW DIFFERENTIAL LOGIC-CIRCUITS FOR THE IMPLEMENTATION OF TERNARY LOGIC SYSTEMS IN CMOS-VLSI WITHOUT PROCESS MODIFICATION
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HUANG, HY; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:43Z |
A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
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CHIN, SY; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:41Z |
REALIZATIONS OF HIGH-ORDER SWITCHED-CAPACITOR FILTERS USING MULTIPLEXING TECHNIQUE
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WU, CY; BOR, JC; JENG, BS |
| 國立交通大學 |
2014-12-08T15:03:37Z |
THE EFFECTS OF IMPURITY BANDS ON THE ELECTRICAL CHARACTERISTICS OF METAL-SEMICONDUCTOR OHMIC CONTACTS
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:37Z |
NEW DESIGN TECHNIQUES FOR A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CURRENT READOUT INTEGRATED-CIRCUIT FOR INFRARED DETECTOR ARRAYS
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WU, CY; HSIEH, CC |
| 國立交通大學 |
2014-12-08T15:03:36Z |
A LOW GLITCH 10-BIT 75-MHZ CMOS VIDEO D/A CONVERTER
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WU, TY; JIH, CT; CHEN, JC; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:36Z |
PRECISE CMOS CURRENT SAMPLE HOLD CIRCUITS USING DIFFERENTIAL CLOCK FEEDTHROUGH ATTENUATION TECHNIQUES
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WU, CY; CHEN, CC; CHO, JJ |
| 國立交通大學 |
2014-12-08T15:03:30Z |
LATERAL TITANIUM SILICIDE GROWTH AND ITS SUPPRESSION USING THE A-SI/TI BILAYER STRUCTURE
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LOU, YS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:27Z |
A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION
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WEN, KS; LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:25Z |
A NOVEL EXTRACTION TECHNIQUE FOR THE EFFECTIVE CHANNEL-LENGTH OF MOSFET DEVICES
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LI, HH; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:24Z |
A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES
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WU, CY; CHEN, CC; CHO, JJ |
Showing items 371-395 of 607 (25 Page(s) Totally)
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