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顯示項目 371-420 / 607 (共13頁)
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機構	日期	題名	作者
國立交通大學	2014-12-08T15:04:41Z	A NEW OXIDATION-RESISTANT COSI2 PROCESS FOR SELF-ALIGNED SILICIDATION (SALICIDE) TECHNOLOGY	LOU, YS; WU, CY; CHENG, HC
國立交通大學	2014-12-08T15:04:34Z	A NEW IV MODEL FOR SHORT GATE-LENGTH MESFETS	CHIN, SP; WU, CY
國立交通大學	2014-12-08T15:04:25Z	DESIGN AND APPLICATION OF PIPELINED DYNAMIC CMOS TERNARY LOGIC AND SIMPLE TERNARY DIFFERENTIAL LOGIC	WU, CY; HUANG, HY
國立交通大學	2014-12-08T15:04:23Z	A NEW GRID-GENERATION METHOD FOR 2-D SIMULATION OF DEVICES WITH NONPLANAR SEMICONDUCTOR SURFACE	CHIN, SP; WU, CY
國立交通大學	2014-12-08T15:04:22Z	A NEW 2D ANALYTIC THRESHOLD-VOLTAGE MODEL FOR FULLY DEPLETED SHORT-CHANNEL SOI MOSFETS	GUO, JY; WU, CY
國立交通大學	2014-12-08T15:04:22Z	THE DESIGN OF FULLY DIFFERENTIAL CMOS OPERATIONAL-AMPLIFIERS WITHOUT EXTRA COMMON-MODE FEEDBACK-CIRCUITS	LU, PH; WU, CY; TSAI, MK
國立交通大學	2014-12-08T15:04:20Z	A NOVEL PHL-EMITTER BIPOLAR-TRANSISTOR - FABRICATION AND CHARACTERIZATION	CHANG, KZ; WU, CY
國立交通大學	2014-12-08T15:04:12Z	NOVEL CHARACTERISTICS OF THE POLYSILICON HIGH-LOW-EMITTER (PHL-EMITTER) BIPOLAR-TRANSISTOR HIGH-CURRENT GAIN AND ZERO ACTIVATION-ENERGY	CHANG, KZ; WU, CY
國立交通大學	2014-12-08T15:04:11Z	CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE	KER, MD; WU, CY
國立交通大學	2014-12-08T15:04:09Z	TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION	KER, MD; WU, CY
國立交通大學	2014-12-08T15:04:09Z	A CHARACTERIZATION TECHNIQUE FOR THE DEGRADATION CHARACTERISTICS OF TI/SI SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS AFTER THERMAL SILICIDATION	LOU, YS; WU, CY
國立交通大學	2014-12-08T15:04:08Z	COMPARATIVE-STUDIES OF GD-ORDERING IN VARIOUS CUPRATE SYSTEMS	HO, JC; WU, CY; LAI, CC; SHIEH, JH; KU, HC
國立交通大學	2014-12-08T15:04:08Z	MAGNETIC-BEHAVIOR IN PR-CONTAINING TL-BASED AND PB-BASED CUPRATES	KU, HC; LAI, CC; SHIEH, JH; LIOU, JW; WU, CY; HO, JC
國立交通大學	2014-12-08T15:04:02Z	A SELF-CONSISTENT CHARACTERIZATION METHODOLOGY FOR SCHOTTKY-BARRIER DIODES AND OHMIC CONTACTS	LOU, YS; WU, CY
國立交通大學	2014-12-08T15:03:57Z	NEW DESIGN METHODOLOGY AND NEW DIFFERENTIAL LOGIC-CIRCUITS FOR THE IMPLEMENTATION OF TERNARY LOGIC SYSTEMS IN CMOS-VLSI WITHOUT PROCESS MODIFICATION	HUANG, HY; WU, CY
國立交通大學	2014-12-08T15:03:43Z	A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES	CHIN, SY; WU, CY
國立交通大學	2014-12-08T15:03:41Z	REALIZATIONS OF HIGH-ORDER SWITCHED-CAPACITOR FILTERS USING MULTIPLEXING TECHNIQUE	WU, CY; BOR, JC; JENG, BS
國立交通大學	2014-12-08T15:03:37Z	THE EFFECTS OF IMPURITY BANDS ON THE ELECTRICAL CHARACTERISTICS OF METAL-SEMICONDUCTOR OHMIC CONTACTS	LOU, YS; WU, CY
國立交通大學	2014-12-08T15:03:37Z	NEW DESIGN TECHNIQUES FOR A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CURRENT READOUT INTEGRATED-CIRCUIT FOR INFRARED DETECTOR ARRAYS	WU, CY; HSIEH, CC
國立交通大學	2014-12-08T15:03:36Z	A LOW GLITCH 10-BIT 75-MHZ CMOS VIDEO D/A CONVERTER	WU, TY; JIH, CT; CHEN, JC; WU, CY
國立交通大學	2014-12-08T15:03:36Z	PRECISE CMOS CURRENT SAMPLE HOLD CIRCUITS USING DIFFERENTIAL CLOCK FEEDTHROUGH ATTENUATION TECHNIQUES	WU, CY; CHEN, CC; CHO, JJ
國立交通大學	2014-12-08T15:03:30Z	LATERAL TITANIUM SILICIDE GROWTH AND ITS SUPPRESSION USING THE A-SI/TI BILAYER STRUCTURE	LOU, YS; WU, CY
國立交通大學	2014-12-08T15:03:27Z	A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION	WEN, KS; LI, HH; WU, CY
國立交通大學	2014-12-08T15:03:25Z	A NOVEL EXTRACTION TECHNIQUE FOR THE EFFECTIVE CHANNEL-LENGTH OF MOSFET DEVICES	LI, HH; WU, CY
國立交通大學	2014-12-08T15:03:24Z	A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES	WU, CY; CHEN, CC; CHO, JJ
國立交通大學	2014-12-08T15:03:22Z	CMOS CURRENT-MODE IMPLEMENTATION OF SPATIOTEMPORAL PROBABILISTIC NEURAL NETWORKS FOR SPEECH RECOGNITION	WU, CY; LIU, RY; JOU, IC
國立交通大學	2014-12-08T15:03:20Z	MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION	KER, MD; WU, CY
國立交通大學	2014-12-08T15:03:20Z	MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION	KER, MD; WU, CY
國立交通大學	2014-12-08T15:03:17Z	A NEW CONSTANT-FIELD SCALING THEORY FOR MOSFETS	MAA, JJ; WU, CY
國立交通大學	2014-12-08T15:03:16Z	COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS	KER, MD; WU, CY
國立交通大學	2014-12-08T15:03:16Z	A SIMPLE AND ACCURATE SIMULATION TECHNIQUE FOR FLASH EEPROM WRITING AND ITS RELIABILITY ISSUE	WEN, KS; WU, CY
國立交通大學	2014-12-08T15:03:14Z	A NEW SIMPLIFIED THRESHOLD-VOLTAGE MODEL FOR N-MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE AND ITS APPLICATION TO MOSFETS MINIATURIZATION	MAA, JJ; WU, CY
國立交通大學	2014-12-08T15:03:14Z	A NEW STRUCTURE OF THE 2-D SILICON RETINA	WU, CY; CHIU, CF
國立交通大學	2014-12-08T15:03:12Z	A CMOS CURRENT-MODE DESIGN OF MODIFIED LEARNING-VECTOR-QUANTIZATION NEURAL NETWORKS	LIU, RY; WU, CY; JOU, IC
國立交通大學	2014-12-08T15:03:01Z	A 2-D ANALYTIC MODEL FOR THE THRESHOLD-VOLTAGE OF FULLY DEPLETED SHORT GATE-LENGTH SI-SOI MESFETS	HOU, CS; WU, CY
國立交通大學	2014-12-08T15:02:57Z	Synthesis of novel triacetal oxa-cage compounds	Wu, HJ; Wu, CY; Lin, CC
國立交通大學	2014-12-08T15:02:54Z	Analog electronic cochlea design using multiplexing switched-capacitor circuits	Bor, JC; Wu, CY
國立交通大學	2014-12-08T15:02:54Z	CMOS current-mode neural associative memory design with on-chip learning	Wu, CY; Lan, JF
國立交通大學	2014-12-08T15:02:49Z	A novel method for extracting the metallurgical channel length of MOSFET's using a single device	Li, HH; Chu, YL; Wu, CY
國立交通大學	2014-12-08T15:02:48Z	A design strategy for short gate length SOI MESFETs	Hou, CS; Wu, CY
國立交通大學	2014-12-08T15:02:45Z	Synthesis of novel triacetal trioxa-cage compounds by ozonolysis of bicyclo[2.2.1]heptenes and bicyclo[2.2.2]octenes	Wu, CY; Lin, CC; Lai, MC; Wu, HJ
國立交通大學	2014-12-08T15:02:44Z	Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI	Ker, MD; Wu, CY; Chang, HH
國立交通大學	2014-12-08T15:02:42Z	Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based transresistance amplifiers	Lu, PH; Wu, CY; Tsai, MK
國立交通大學	2014-12-08T15:02:40Z	A novel two-step etching process for reducing plasma-induced oxide damage	You, KF; Wu, CY
國立交通大學	2014-12-08T15:02:40Z	The design of CMOS continuous-time VHF current and voltage-mode lowpass filters with Q-enhancement circuits	Wu, CY; Hsu, HS
國立交通大學	2014-12-08T15:02:37Z	A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFET's	Jean, YS; Wu, CY
國立交通大學	2014-12-08T15:02:35Z	Synthesis of tetraacetal tetraoxa-cage compounds with alkyl substituents at different sites of the oxa-cage skeleton	Lin, RL; Wu, CY; Chern, JH; Wu, HJ
國立交通大學	2014-12-08T15:02:27Z	A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter	Chin, SY; Wu, CY
國立交通大學	2014-12-08T15:02:23Z	Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC	Ker, MD; Wu, CY; Cheng, T; Chang, HH
國立交通大學	2014-12-08T15:02:13Z	Low-temperature characteristics of well-type guard rings in epitaxial CMOS	Huang, CY; Chen, MJ; Jeng, JK; Wu, CY

顯示項目 371-420 / 607 (共13頁)
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