|
English
|
正體中文
|
简体中文
|
总笔数 :0
|
|
造访人次 :
51798332
在线人数 :
1038
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"wu cy"的相关文件
显示项目 151-160 / 607 (共61页)
<< < 11 12 13 14 15 16 17 18 19 20 > >>
每页显示[10|25|50]项目
| 國立交通大學 |
2014-12-08T15:49:03Z |
Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
|
Ker, MD; Wu, CY; Huang, CC; Chen, TY |
| 國立交通大學 |
2014-12-08T15:49:00Z |
A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer
|
Hsiao, SY; Wu, CY |
| 國立交通大學 |
2014-12-08T15:48:51Z |
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA
|
Hsieh, CC; Wu, CY; Sun, TP; Jih, FW; Cherng, YT |
| 國立交通大學 |
2014-12-08T15:47:36Z |
An efficient transient modeling for 3-D multilevel interconnections in a stratified dielectric medium
|
Wu, CY; Hou, HM |
| 國立交通大學 |
2014-12-08T15:47:31Z |
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
|
Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:47:29Z |
An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor
|
Chen, HL; Wu, CY |
| 國立交通大學 |
2014-12-08T15:47:06Z |
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications
|
Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:46:55Z |
A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector
|
Jiang, HC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:46:46Z |
Synthesis of pentaoxa[5]peristylanes
|
Wu, HJ; Wu, CY |
| 國立交通大學 |
2014-12-08T15:46:44Z |
A novel transient simulation for 3-D multilevel interconnections on complex topography
|
Hou, HM; Sheen, CS; Wu, CY |
显示项目 151-160 / 607 (共61页)
<< < 11 12 13 14 15 16 17 18 19 20 > >>
每页显示[10|25|50]项目
|
