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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"wu cy"的相關文件
顯示項目 151-160 / 607 (共61頁)
<< < 11 12 13 14 15 16 17 18 19 20 > >>
每頁顯示[10|25|50]項目
| 國立交通大學 |
2014-12-08T15:49:03Z |
Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
|
Ker, MD; Wu, CY; Huang, CC; Chen, TY |
| 國立交通大學 |
2014-12-08T15:49:00Z |
A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer
|
Hsiao, SY; Wu, CY |
| 國立交通大學 |
2014-12-08T15:48:51Z |
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA
|
Hsieh, CC; Wu, CY; Sun, TP; Jih, FW; Cherng, YT |
| 國立交通大學 |
2014-12-08T15:47:36Z |
An efficient transient modeling for 3-D multilevel interconnections in a stratified dielectric medium
|
Wu, CY; Hou, HM |
| 國立交通大學 |
2014-12-08T15:47:31Z |
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
|
Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:47:29Z |
An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor
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Chen, HL; Wu, CY |
| 國立交通大學 |
2014-12-08T15:47:06Z |
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications
|
Tseng, YK; Wu, CY |
| 國立交通大學 |
2014-12-08T15:46:55Z |
A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector
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Jiang, HC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:46:46Z |
Synthesis of pentaoxa[5]peristylanes
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Wu, HJ; Wu, CY |
| 國立交通大學 |
2014-12-08T15:46:44Z |
A novel transient simulation for 3-D multilevel interconnections on complex topography
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Hou, HM; Sheen, CS; Wu, CY |
顯示項目 151-160 / 607 (共61頁)
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每頁顯示[10|25|50]項目
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