|
English
|
正體中文
|
简体中文
|
总笔数 :0
|
|
造访人次 :
51798334
在线人数 :
1040
教育部委托研究计画 计画执行:国立台湾大学图书馆
|
|
|
"wu cy"的相关文件
显示项目 401-410 / 607 (共61页)
<< < 36 37 38 39 40 41 42 43 44 45 > >>
每页显示[10|25|50]项目
| 國立交通大學 |
2014-12-08T15:03:16Z |
A SIMPLE AND ACCURATE SIMULATION TECHNIQUE FOR FLASH EEPROM WRITING AND ITS RELIABILITY ISSUE
|
WEN, KS; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:14Z |
A NEW SIMPLIFIED THRESHOLD-VOLTAGE MODEL FOR N-MOSFETS WITH NONUNIFORMLY DOPED SUBSTRATE AND ITS APPLICATION TO MOSFETS MINIATURIZATION
|
MAA, JJ; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:14Z |
A NEW STRUCTURE OF THE 2-D SILICON RETINA
|
WU, CY; CHIU, CF |
| 國立交通大學 |
2014-12-08T15:03:12Z |
A CMOS CURRENT-MODE DESIGN OF MODIFIED LEARNING-VECTOR-QUANTIZATION NEURAL NETWORKS
|
LIU, RY; WU, CY; JOU, IC |
| 國立交通大學 |
2014-12-08T15:03:01Z |
A 2-D ANALYTIC MODEL FOR THE THRESHOLD-VOLTAGE OF FULLY DEPLETED SHORT GATE-LENGTH SI-SOI MESFETS
|
HOU, CS; WU, CY |
| 國立交通大學 |
2014-12-08T15:02:57Z |
Synthesis of novel triacetal oxa-cage compounds
|
Wu, HJ; Wu, CY; Lin, CC |
| 國立交通大學 |
2014-12-08T15:02:54Z |
Analog electronic cochlea design using multiplexing switched-capacitor circuits
|
Bor, JC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:02:54Z |
CMOS current-mode neural associative memory design with on-chip learning
|
Wu, CY; Lan, JF |
| 國立交通大學 |
2014-12-08T15:02:49Z |
A novel method for extracting the metallurgical channel length of MOSFET's using a single device
|
Li, HH; Chu, YL; Wu, CY |
| 國立交通大學 |
2014-12-08T15:02:48Z |
A design strategy for short gate length SOI MESFETs
|
Hou, CS; Wu, CY |
显示项目 401-410 / 607 (共61页)
<< < 36 37 38 39 40 41 42 43 44 45 > >>
每页显示[10|25|50]项目
|
