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顯示項目 301-350 / 607 (共13頁)
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機構	日期	題名	作者
國立交通大學	2014-12-08T15:06:13Z	AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATION	WU, CY; DAIH, YW
國立交通大學	2014-12-08T15:06:13Z	A NEW THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY BURIED-CHANNEL MOSFETS	WU, CY; HSU, KC
國立交通大學	2014-12-08T15:06:13Z	MOBILITY MODELS FOR THE IV CHARACTERISTICS OF BURIED-CHANNEL MOSFETS	WU, CY; HSU, KC
國立交通大學	2014-12-08T15:06:12Z	SUPERIOR CHARACTERISTICS OF NITRIDIZED THERMAL OXIDE GROWN ON POLYCRYSTALLINE SILICON	CHEN, CF; WU, CY
國立交通大學	2014-12-08T15:06:11Z	AN EFFICIENT METHOD FOR CALCULATING THE DC TRIGGERING CURRENTS IN CMOS LATCH-UP	CHEN, MJ; WU, CY
國立交通大學	2014-12-08T15:06:11Z	A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES	CHEN, MJ; WU, CY
國立交通大學	2014-12-08T15:06:11Z	AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATION	WU, CY; HUANG, GS; CHEN, HH
國立交通大學	2014-12-08T15:06:11Z	AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS	CHEN, MJ; WU, CY
國立交通大學	2014-12-08T15:06:09Z	AN ENVIRONMENT-INSENSITIVE TRILAYER STRUCTURE FOR TITANIUM SILICIDE FORMATION	LIN, MZ; YU, YCS; WU, CY
國立交通大學	2014-12-08T15:06:09Z	A CHARACTERIZATION MODEL FOR RAMP-VOLTAGE-STRESSED IV CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE	CHEN, CF; WU, CY
國立交通大學	2014-12-08T15:06:09Z	CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERS	CHEN, MJ; WU, CY
國立交通大學	2014-12-08T15:06:08Z	A NEW OXIDATION-RESISTANT SELF-ALIGNED TISI2 PROCESS	TSENG, HH; WU, CY
國立交通大學	2014-12-08T15:06:07Z	A CHARACTERIZATION MODEL FOR CONSTANT CURRENT STRESSED VOLTAGE-TIME CHARACTERISTICS OF THIN THERMAL OXIDES GROWN ON SILICON SUBSTRATE	CHEN, CF; WU, CY
國立交通大學	2014-12-08T15:06:06Z	THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC	WU, CY; WANG, JS; TSAI, MK
國立交通大學	2014-12-08T15:06:06Z	A SIMPLE TECHNIQUE FOR MEASURING THE INTERFACE-STATE DENSITY OF THE SCHOTTKY-BARRIER DIODES USING THE CURRENT-VOLTAGE CHARACTERISTICS	TSENG, HH; WU, CY
國立交通大學	2014-12-08T15:06:05Z	THE DISTORTION OF THE INTERFACE-STATE SPECTRUM DUE TO NONEQUILIBRIUM OCCUPANCY OF THE INTERFACE STATES AT THE METAL-SEMICONDUCTOR INTERFACE	TSENG, HH; WU, CY
國立交通大學	2014-12-08T15:06:05Z	THE EFFECTS OF THERMAL NITRIDATION CONDITIONS ON THE RELIABILITY OF THIN NITRIDED OXIDE-FILMS	TSAI, HH; WU, LC; WU, CY; HU, CM
國立交通大學	2014-12-08T15:06:05Z	A NEW STRUCTURE-ORIENTED MODEL FOR WELL RESISTANCE IN CMOS LATCHUP STRUCTURES	CHEN, MJ; SZE, SC; CHEN, HH; WU, CY
國立交通大學	2014-12-08T15:06:05Z	A SIMPLE INTERFACIAL-LAYER MODEL FOR THE NONIDEAL IV AND C-V CHARACTERISTICS OF THE SCHOTTKY-BARRIER DIODE	TSENG, HH; WU, CY
國立交通大學	2014-12-08T15:06:04Z	AN ANALYTIC IV MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICES	HUANG, GS; WU, CY
國立交通大學	2014-12-08T15:06:04Z	SUPERIOR CHARACTERISTICS OF THERMAL OXIDE LAYERS GROWN ON AMORPHOUS-SILICON FILMS	WU, CY; CHEN, CF
國立交通大學	2014-12-08T15:06:03Z	A NEW APPROACH TO ANALYTICALLY SOLVING THE TWO-DIMENSIONAL POISSON EQUATION AND ITS APPLICATION IN SHORT-CHANNEL MOSFET MODELING	LIN, PS; WU, CY
國立交通大學	2014-12-08T15:06:03Z	A SIMPLIFIED COMPUTER-ANALYSIS FOR NORMAL-WELL GUARD RING EFFICIENCY IN CMOS CIRCUITS	CHEN, MJ; WU, CY
國立交通大學	2014-12-08T15:06:03Z	THE DIELECTRIC RELIABILITY OF INTRINSIC THIN SIO2-FILMS THERMALLY GROWN ON A HEAVILY DOPED SI SUBSTRATE - CHARACTERIZATION AND MODELING	CHEN, CF; WU, CY; LEE, MK; CHEN, CN
國立交通大學	2014-12-08T15:06:03Z	TRANSPORT-PROPERTIES OF THERMAL OXIDE-FILMS GROWN ON POLYCRYSTALLINE SILICON - MODELING AND EXPERIMENTS	WU, CY; CHEN, CF
國立交通大學	2014-12-08T15:06:01Z	THE EFFECTS OF THERMAL SILICIDATION ON THE CURRENT TRANSPORT CHARACTERISTICS OF TI/(111)SI SCHOTTKY-BARRIER CONTACTS	TSENG, HH; WU, CY
國立交通大學	2014-12-08T15:06:00Z	A NEW METHOD FOR DETERMINING THE TERMINAL SERIES RESISTANCES AND HIGH-INJECTION COEFFICIENT OF BIPOLAR-TRANSISTORS IN CMOS INTEGRATED-CIRCUITS FOR COMPUTER-AIDED CIRCUIT MODELING	YANG, YH; WU, CY; CHEN, WY
國立交通大學	2014-12-08T15:06:00Z	GENERAL EXPERIMENTAL-METHOD OF PARAMETER EXTRACTION FOR CMOS TIMING MACROMODELS	WU, CY; JANG, WY; WU, HJ
國立交通大學	2014-12-08T15:05:59Z	INTEGRAL-EQUATION SOLUTION FOR HYPERBOLIC HEAT-CONDUCTION WITH SURFACE RADIATION	WU, CY
國立交通大學	2014-12-08T15:05:59Z	TIMING MACROMODELS FOR CMOS STATIC SET RESET LATCHES AND THEIR APPLICATIONS	WU, CY; LI, C; HWANG, JS
國立交通大學	2014-12-08T15:05:57Z	A NEW EXPERIMENTAL-METHOD TO DETERMINE THE SATURATION VOLTAGE OF A SMALL-GEOMETRY MOSFET	JANG, WY; WU, CY; WU, HJ
國立交通大學	2014-12-08T15:05:57Z	A NEW LATERAL GROWTH FREE FORMATION TECHNIQUE FOR TITANIUM SILICIDE USING THE SI/W/TI TRILAYER STRUCTURE	LIN, MZ; WU, CY
國立交通大學	2014-12-08T15:05:56Z	LOW-POWER DYNAMIC TERNARY LOGIC	WANG, JS; WU, CY; TSAI, MK
國立交通大學	2014-12-08T15:05:55Z	COBALT SILICIDE INTERCONNECTION FROM A SI/W/CO TRILAYER STRUCTURE	LIN, MZ; WU, CY
國立交通大學	2014-12-08T15:05:53Z	NEW MONOLITHIC SWITCHED-CAPACITOR DIFFERENTIATORS WITH GOOD NOISE REJECTION	WU, CY; YU, TC; CHANG, SS
國立交通大學	2014-12-08T15:05:51Z	THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS	YANG, YH; WU, CY
國立交通大學	2014-12-08T15:05:50Z	NOVEL DYNAMIC CMOS LOGIC FREE FROM PROBLEMS OF CHARGE SHARING AND CLOCK SKEW	WANG, JS; WU, CY; TSAI, MK
國立交通大學	2014-12-08T15:05:49Z	AN IMPROVED PROPAGATION-DELAY-TIME FORMULA FOR THE SUB-MICRON N-MOS INVERTER	WU, CY
國立交通大學	2014-12-08T15:05:48Z	A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS	YANG, YH; WU, CY
國立交通大學	2014-12-08T15:05:48Z	A NEW TWIN-WELL CMOS PROCESS USING NITRIDIZED-OXIDE-LOCOS (NOLOCOS) ISOLATION TECHNOLOGY	TSAI, HH; YU, CL; WU, CY
國立交通大學	2014-12-08T15:05:48Z	PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS	WU, CY; HWANG, JS
國立交通大學	2014-12-08T15:05:48Z	CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS	WANG, JS; WU, CY; TSAI, MK
國立交通大學	2014-12-08T15:05:45Z	ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES	YANG, YH; WU, CY
國立交通大學	2014-12-08T15:05:45Z	A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC	WU, CY; LIN, YT
國立交通大學	2014-12-08T15:05:40Z	REALIZATIONS OF IIR FIR AND N-PATH FILTERS USING A NOVEL SWITCHED-CAPACITOR TECHNIQUE	YU, TC; WU, CY; CHANG, SS
國立交通大學	2014-12-08T15:05:39Z	A NEW ALGORITHM FOR STEADY-STATE 2-D NUMERICAL-SIMULATION OF MOSFETS	PERNG, RK; WU, CY
國立交通大學	2014-12-08T15:05:37Z	THE SIGNAL DELAY IN INTERCONNECTION LINES CONSIDERING THE EFFECTS OF SMALL-GEOMETRY CMOS INVERTERS	SHIAU, MC; WU, CY
國立交通大學	2014-12-08T15:05:37Z	A QUASI-2-DIMENSIONAL ANALYTICAL MODEL FOR THE TURN-ON CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORS	LIN, PS; GUO, JY; WU, CY
國立交通大學	2014-12-08T15:05:37Z	THE EFFECT OF GATE ELECTRODES USING TUNGSTEN SILICIDES AND OR POLYSILICON ON THE DIELECTRIC CHARACTERISTICS OF VERY THIN OXIDES	CHENG, HC; CHAO, CY; SU, WD; CHANG, SW; LEE, MK; WU, CY
國立交通大學	2014-12-08T15:05:35Z	MOS DEVICE PARAMETER OPTIMIZATION BASED ON TRANSIENT TRAJECTORY CONSIDERATIONS	WU, CY; JANG, WY; LIU, ID

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